Neural Network Hardware Recognition Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The recognition stage in neural networks, when implemented with software, faces challenges of high processing time and power consumption due to the complexity of hardware configurations required for multi-layer neural networks with numerous parameters and computations.
Innovation Solution
A recognition device is designed with a series of computation layers using digital-to-time conversion circuits and time-to-digital conversion circuits to simplify the hardware configuration, performing computation using time signals and threshold value processing to reduce power consumption and enhance processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the recognition stage is implemented with software, then flexibility and ease of operation are maintained, but processing time increases and power consumption increases
Solution Approach 1:
The patent replaces software-based computation with a hardware neural network processing system that uses electrical signals and circuit operations to perform recognition tasks, thereby reducing processing time while maintaining operational flexibility through configurable circuit designs
Solution Approach 2:
The patent introduces a dedicated hardware processing unit as an intermediary between input data and output recognition results, which specializes in performing neural network computations efficiently through purpose-built circuitry including multiplication units and accumulation units
2Speed
If the recognition stage is implemented with hardware, then processing speed improves, but device complexity increases due to numerous parameters and computations
Solution Approach 1:
The patent divides the neural network processing into distinct functional segments including input reception units, multiplication units for computing products of inputs and weights, accumulation units for summing products, and output generation units, allowing each segment to be optimized independently while reducing overall system complexity
Solution Approach 2:
The patent designs universal processing units that can handle multiple neural network operations including multiplication, accumulation, and threshold comparison through configurable circuit elements, reducing the need for separate dedicated circuits for each operation and thereby simplifying the overall hardware configuration
3Speed
If the recognition stage is implemented with hardware, then processing speed improves, but power consumption increases
Solution Approach 1:
The patent employs parameter optimization techniques including adjusting weight values, threshold values, and circuit operating parameters to achieve efficient processing with reduced power consumption, allowing the system to maintain high processing speed while minimizing energy usage through careful parameter selection
Data Source
AI summary
According to one embodiment, a processing device is configured to process input data formed of a plurality of input digital values. The processing device has a plurality of computation layers connected in series. Each of the computation layers has a plurality of computation devices. Each of the plurality of computation devices in the computation layer of a first stage is configured to generate a digital value from the input digital values and weight coefficients defined in advance. The weight coefficients are applied to each of the input digital values. Each of the plurality of computation devices of the computation layer of a second or subsequent stage is configured to generate a new digital value from the digital values generated by the computation devices of the computation layer of the previous stage and weight coefficients defined in advance. The weight coefficients are applied to each of the digital values.