Neural Network Hardware Building Block Conversion
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Solution Overview
Problem
Deep neural networks (DNNs) face challenges in deployment on energy and resource-constrained hardware due to their large memory and computational footprints, with existing strategies like fixed hardware architectures acting as barriers to optimizations and requiring non-trivial compilers for mapping and scheduling.
Innovation Solution
The techniques involve defining hardware building blocks and neuron equivalents, allowing DNNs to be customized during training to directly map to efficient programmable device hardware, exposing the programmable device fabric to a machine learning framework for training with backpropagation, and converting the network into a netlist of hardware building blocks for efficient implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed hardware architecture is used to map DNN neurons, then the hardware implementation is simplified, but the DNN cannot take full advantage of the programmable device fabric and requires non-trivial optimizing compilers
Solution Approach 1:
The patent makes the hardware architecture dynamic by allowing the neural network topology to be directly mapped to the programmable device fabric without a fixed intermediate architecture. The hardware configuration adapts dynamically to match the trained network structure, eliminating the need for fixed overlay architectures and complex compilation steps while maximizing fabric utilization.
Solution Approach 2:
The patent extracts and removes the fixed hardware architecture interface layer that acts as a barrier between the DNN and the programmable device fabric. By eliminating this intermediate layer, the neural network can directly utilize the full capabilities of the fabric, improving compute efficiency without requiring complex optimizing compilers to bridge the gap.
2Measurement precision
If the size of DNNs is increased to improve prediction capabilities, then accuracy is improved, but memory and computational footprints scale up making deployment difficult in constrained hardware
Solution Approach 1:
The patent changes the parameters of the neural network by exposing the building blocks of the programmable device fabric directly to the machine learning framework. This allows the network to be customized during training with parameters optimized for the target hardware, enabling large accurate networks to be deployed on resource-constrained devices through direct hardware-aware training rather than post-training optimization.
Solution Approach 2:
The patent performs hardware optimization preliminarily during the training phase rather than as a post-processing step. By integrating hardware constraints and capabilities directly into the training process, the network is pre-optimized for the target device, reducing the computational and memory footprint before deployment without sacrificing accuracy.
3Quantity of substance
If trained quantization methods are used to reduce workload, then compute and memory cost is reduced, but the network requires conversion from floating-point to quantized formats
Solution Approach 1:
The patent performs quantization preliminarily during the training process by exposing the target hardware building blocks directly to the machine learning framework. This allows the network to be trained with quantized weights and activations from the outset, eliminating the need for separate post-training conversion steps and reducing the complexity of quantization implementation.
Data Source
AI summary
An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.