Neural Network Instruction Processing Apparatus for Acceleration
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Solution Overview
Problem
Current neural network acceleration units face inefficiencies in processing neural network models due to limitations in instruction set architecture, leading to suboptimal execution of neural network operations such as matrix multiplication, convolution, and depth-wise convolution.
Innovation Solution
An instruction processing apparatus with a dedicated instruction set architecture that includes a selector, parser, and operation circuit, which processes and executes instruction sequences for neural network operations, utilizing predefined instructions for data loading, multiplication accumulation, and scalar calculations, and supports different neural network applications by varying instruction pipelines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a general-purpose instruction set architecture is used in the acceleration unit, then the device can be simpler and more versatile, but the execution efficiency of neural network operations deteriorates due to suboptimal instruction processing
Solution Approach 1:
The instruction processing apparatus is segmented into specialized functional modules: a parser for decoding instructions, a register file for operand storage, and an operation circuit for executing specific neural network operations. This segmentation allows each module to be optimized for its specific function, improving overall execution efficiency while maintaining manageable complexity through modular design.
Solution Approach 2:
The system changes the parameters of the instruction set architecture from general-purpose to specialized parameters optimized for neural network operations. The instruction format includes specific fields for neural network operations (e.g., operation type, input/output buffer identifiers, activation function selection), enabling efficient processing of matrix multiplication, convolution, and other neural network primitives without requiring complex general-purpose instruction decoding.
2Productivity
If more data is transferred between the acceleration unit and external memory, then more operations can be performed, but the execution efficiency deteriorates due to increased data transfer overhead
Solution Approach 1:
The system performs preliminary actions by pre-loading input data into on-chip buffers (input buffer, weight buffer) before the actual computation begins. The instruction format includes buffer identifiers that enable the operation circuit to directly access pre-positioned data, eliminating the need for frequent external memory accesses during computation and reducing data transfer overhead.
Solution Approach 2:
On-chip buffers serve as intermediaries between external memory and the operation circuit. These buffers (input buffer, weight buffer, output buffer) temporarily store data locally, allowing the operation circuit to perform multiple operations on cached data without repeated external memory accesses, thus reducing data transfer time while maintaining high throughput.
3Adaptability or versatility
If a simplified instruction processing approach is used, then the device complexity is reduced, but the adaptability to different neural network applications deteriorates
Solution Approach 1:
The operation circuit is designed with universal functionality to handle multiple neural network operations through a unified instruction format. The same hardware circuit can perform matrix multiplication, convolution, depth-wise convolution, and other operations by interpreting different operation codes in the instruction stream, eliminating the need for separate dedicated circuits for each operation and maintaining adaptability without proportionally increasing complexity.
Solution Approach 2:
The system introduces dynamic configurability through the instruction format, which includes fields for selecting operation types, activation functions, and buffer configurations. This allows the operation circuit to dynamically adapt its behavior based on the current neural network application requirements, providing versatility while maintaining a relatively simple fixed hardware structure that can be reconfigured through software instructions.
Data Source
AI summary
An instruction processing apparatus is disclosed. The instruction processing apparatus includes: a selector is configured to parse out a command type and a buffer identifier from a command, provide received data and the buffer identifier to a parser if the command type is configuration, and provide the received data and the buffer identifier to an operation circuit if the command type is execution; the parser is configured to parse out an instruction sequence from the data, store the instruction sequence into an instruction buffer corresponding to the buffer identifier, and store an operand of each instruction into a register file; and the operation circuit is configured to drive the instruction buffer to execute each instruction and generate a control signal, and trigger a plurality of execution units to perform operations based on received control signals and operands. The apparatus may be dedicated to processing various neural network applications.