Integrated Circuit for Neural Network Layer Multiplexing
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Solution Overview
Problem
Existing convolutional neural networks face high hardware costs and resource wastage due to the separate calculation requirements for convolutional and full connection layers, where the full connection layer's smaller calculation load leads to idle resources.
Innovation Solution
An integrated circuit design that includes a data storage circuit, a weight storage circuit, and an operation circuit, allowing for simultaneous calculation of convolutional and full connection layers by alternating between different time periods for each layer's operations, utilizing a data memory, weight memory, selectors, FIFO memories, multipliers, and adders to perform operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two sets of independent hardware are used to calculate convolutional layer and full connection layer separately, then parallel calculation is achieved, but hardware resources are wasted due to idle capacity in full connection layer
Solution Approach 1:
The patent merges the calculation hardware for convolutional layer and full connection layer into a single shared resource pool. The same array units, accumulators, and control logic are reused alternately for both layer types through time-division multiplexing, eliminating the need for separate independent hardware sets while maintaining parallel processing capability.
Solution Approach 2:
The patent implements periodic action by alternating between convolutional layer calculations and full connection layer calculations in time-division slots. The hardware switches between different computational tasks in a periodic manner, allowing the same resources to serve multiple functions at different time intervals, thus avoiding resource idle time while preventing resource contention.
2Reliability
If separate independent hardware is allocated for convolutional and full connection layers, then calculation independence is ensured, but hardware cost increases
Solution Approach 1:
The patent introduces dynamic resource allocation where the hardware configuration adapts based on the current computational task. Through dynamic control signals, the same physical hardware can reconfigure its operational mode to match the requirements of either convolutional or full connection layer calculations, ensuring calculation independence through logical isolation rather than physical separation.
Solution Approach 2:
The patent designs universal calculation units that can perform both convolutional operations and full connection operations. The array units, accumulators, and data pathways are engineered with multi-functional capabilities, allowing a single hardware instance to serve multiple computational purposes, thereby reducing overall hardware cost while maintaining the reliability needed for independent calculations.
Data Source
AI summary
An integrated circuit includes a data storage circuit, a weight storage circuit, and an operation circuit. The data storage circuit stores, according to a preset control instruction, gray-scale value data of an image in a first preset time period; the weight storage circuit stores a data weight corresponding to the gray-scale value data in the first preset time period; the operation circuit carries out an operation on the gray-scale value data and the data weight in the first preset time period and outputs first data; the data storage circuit further stores the first data according to the preset control instruction in a second preset time period; the weight storage circuit further stores the data weight corresponding to the first data in the second preset time period; the operation circuit carries out an operation on the first data and the data weight in the second time period and outputs second data.