Neural Network Processing Device Matrix Operation Segmentation
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Solution Overview
Problem
Current computer systems using neural networks face inefficiencies in calculation processing, particularly in image recognition tasks, due to the high computational load required for convolutional operations, which can lead to increased processor load and reduced processing speed.
Innovation Solution
A processing device comprising multiple circuits that execute specific matrix operations on input data and filters, utilizing pre-processing and post-processing matrices to reduce the calculation load by performing equivalent product-sum operations with a stride value of 2, thereby decreasing the computational requirements for convolutional neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional convolutional operations are used for image recognition, then processing accuracy is maintained, but computational load increases and processing speed decreases
Solution Approach 1:
The processing device is divided into multiple independent circuits (first circuit, second circuit, third circuit, fourth circuit), each handling specific matrix operations. This segmentation allows parallel processing of different parts of the convolution operation, reducing overall computational load and increasing processing speed while maintaining recognition accuracy.
Solution Approach 2:
The first and second circuits perform pre-processing operations on input data and filter data respectively before the main convolution operation. By preparing data in advance through preliminary matrix operations, the subsequent product-sum operation requires fewer calculations, thereby reducing computational load while preserving processing accuracy.
2Measurement precision
If standard convolution operations are performed, then processing accuracy is maintained, but calculation amount increases
Solution Approach 1:
The invention changes the parameters of the convolution operation by using specific matrix dimensions (5×5 input data, 3×3 filter) and applying predetermined matrices in the first and second circuits. This parameter transformation reduces the number of calculations required in the product-sum operation while maintaining the same recognition accuracy through equivalent mathematical operations.
Solution Approach 2:
The first and second circuits act as intermediary processing stages that transform input data and filter data into intermediate representations. These intermediary operations use predetermined matrices to pre-process the data, reducing the complexity of the subsequent convolution operation and decreasing the overall calculation amount while preserving accuracy.
3Reliability
If high computational load is accepted, then processing accuracy is maintained, but processor load increases
Solution Approach 1:
By segmenting the processing device into multiple specialized circuits, each handling specific matrix operations, the invention distributes the computational load across multiple units. This segmentation maintains processing accuracy through dedicated function execution while reducing the burden on any single processor, effectively managing device complexity.
Solution Approach 2:
The processing device uses a universal approach by applying predetermined matrices and standardized product-sum operations across different input data and filter combinations. This multi-functional design allows the same circuit architecture to handle various convolution operations efficiently, maintaining accuracy while reducing overall processor load through reusable computational patterns.
Data Source
AI summary
According to one embodiment, a processing device includes: a first circuit configured to execute first processing using a first matrix to first data of a size of 5×5 within input data to generate second data; a second circuit configured to execute second processing using a second matrix to third data of a size of 3×3 to generate fourth data; a third circuit configured to execute a product-sum operation on the second data and the fourth data; and a fourth circuit configured to execute third processing using a third matrix on a result of the product-sum operation on the second data and the fourth data to obtain a first value corresponding to a result of a product-sum operation on the first data and the third data.