Neural Network Circuit Using Memory Array Integration
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Solution Overview
Problem
Existing neural network computation circuits face challenges in achieving large-scale integration due to increased circuit size and limited number of mountable neurons, as they require multiple cores and peripheral circuitry to connect neurons across various layers.
Innovation Solution
A neural network computation circuit with a non-volatile semiconductor memory element, featuring a word line drive circuit, column selection circuit, computation circuit, output holding circuit, network configuration information holding circuit, and control circuit, which manages connection weight coefficients and network configuration information to perform computations across multiple layers using a single memory array, allowing for high integration and reconfiguration of neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple cores and peripheral circuitry are used to connect neurons across various layers, then the neural network can be configured with any given number of layers and nodes, but the circuit size increases and the number of mountable neurons is limited
Solution Approach 1:
The patent merges the memory array and computation circuit into a single integrated structure where memory cells are arranged in a matrix with word lines and bit lines. The computation circuit directly accesses memory cells through these lines, eliminating the need for separate core-connecting circuits. This integration allows neurons to be connected across multiple layers without increasing peripheral circuitry, as the memory array itself serves as the interconnection medium.
Solution Approach 2:
The memory array serves multiple functions: it stores connection weight coefficients, acts as the interconnection medium between neurons across layers, and provides the computational substrate. The same memory cells and wiring are used for both data storage and data transmission, eliminating the need for dedicated connecting circuits. This multi-functionality allows the system to handle neural networks with any number of layers and nodes without proportionally increasing circuit size.
2Ease of manufacture
If the number of mountable neurons is determined based on the size of peripheral circuitry, then core-connecting circuits can be mounted, but it is difficult to achieve large-scale integration of neurons
Solution Approach 1:
The patent combines the storage function and interconnection function into a single memory array structure. Instead of having separate core-connecting circuits that limit the number of mountable neurons, the memory array's word lines and bit lines provide universal access to all memory cells. This allows a much larger number of neurons to be integrated, as the interconnection capacity scales with the memory array size rather than being constrained by peripheral circuitry.
3Use of energy by moving object
If connection weight coefficients are stored in non-volatile memory elements, then low power consumption is achieved, but the circuit requires complex control for managing network configuration information
Solution Approach 1:
The memory array is organized as a self-contained computational substrate where the address decoders and sense amplifiers are integrated directly with the memory cells. This self-service architecture allows the memory array to manage its own addressing and data retrieval operations without requiring complex external control circuits. The word line drive circuit and column selection circuit work directly with the memory array structure, simplifying the overall control architecture while maintaining low power consumption through non-volatile storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient computation of neural networks with many neurons and layers on a small area, allowing for the integration of a large number of neurons and dynamic reconfiguration of network structures using the same memory array, thereby facilitating practical applications in AI technologies.
Implementation Method 1
variable resistance non-volatile memories capable of setting analog resistance values (conductances)
Implementation Method 2
analog current values flowing in the non-volatile memory elements
Data Source
AI summary
Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.