Multi-Core Neural Network Accelerator with Shared ALU
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Solution Overview
Problem
Existing neural network accelerators face inefficiencies due to single-core designs, which hinder performance and operating speed in processing complex operations, particularly in machine learning applications requiring high parallelism and energy efficiency.
Innovation Solution
A multi-core design is introduced in the neural network processing system, comprising on-chip storage, an address index module, and multiple core processing modules for vector operations, along with an ALU module for non-linear operations, allowing for shared or independent storage and improved parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single-core design is used in neural network processing, then device complexity is reduced, but operating speed and processing throughput deteriorate
Solution Approach 1:
The processing module is divided into multiple independent core processing modules (first core processing module, second core processing module, etc.), each capable of independently executing vector operations. This segmentation enables parallel processing of different feature maps or data batches, thereby increasing operating speed and throughput while maintaining manageable device complexity through modular architecture
Solution Approach 2:
Multiple core processing modules are combined to work together on the same neural network processing task. The cores share common resources including the multiplication and accumulation module, on-chip storage medium, and control logic, allowing them to process different portions of the input data simultaneously and merge their results to produce the final output
2Productivity
If multiple core processing modules are introduced, then processing throughput is improved, but device complexity increases
Solution Approach 1:
Each core processing module is designed as a universal unit that can process any feature map or data batch through the same vector operations. The multiplication and accumulation module serves all cores with the same functional capabilities, reducing the need for duplicate specialized hardware and thereby controlling device complexity while maintaining high processing throughput
Solution Approach 2:
The core processing modules are nested within a hierarchical architecture where they share common resources (multiplication and accumulation module, on-chip storage, control units). This nested structure allows efficient resource utilization and reduces overall device complexity compared to having completely independent processing units for each core
3Use of energy by moving object
If vector multiplication and addition operations are distributed across multiple cores, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The computation workload is segmented and distributed across multiple core processing modules, allowing energy-consuming operations to be performed in parallel. This segmentation reduces the energy burden on any single core and enables more operations to be completed within the same energy budget, improving overall energy efficiency while maintaining a manageable device architecture through the use of identical modular units
Data Source
AI summary
The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.