Neural Network Processing Element Array Mapping Orders

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Solution Overview

Problem

Conventional neural network accelerators face challenges in utilizing processing elements efficiently due to discarded columns during depthwise convolution operations and have low scalability with variable latency multiplications.

Innovation Solution

A neural network operation apparatus with a processing element array and a controller that maps portions of the input feature map and weight matrix to processing elements, allowing for efficient multiplexing and shifting operations, and reorders weight matrices for variable latency scenarios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a conventional two-dimensional processing element array is used for depthwise convolution operations, then the processing element array can be implemented with simple architecture, but the utilization of processing elements decreases due to discarded columns

Engineering Contradiction:
Improveprocessing element array architectureVSAvoidprocessing element utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent transitions from a conventional two-dimensional processing element array to a three-dimensional processing element array by adding a channel dimension. This allows the processing elements to be arranged in a cubic configuration where processing elements in different channels can be simultaneously activated, thereby utilizing all processing elements effectively during depthwise convolution operations without discarding any columns.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If an architecture for multiplications with variable latency is used, then the accelerator can handle variable latency scenarios, but scalability is low when the number of MAC operators is large

Engineering Contradiction:
Improvevariable latency handling capabilityVSAvoidscalability
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent implements a dynamic scheduling mechanism in the controller that can adaptively assign processing elements to operations based on variable latency requirements. The controller dynamically determines the activation timing of processing elements in different channels, allowing the system to handle variable latency scenarios while maintaining high scalability by efficiently managing a large number of MAC operators through flexible resource allocation.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the number of processing elements is increased to improve utilization, then processing capability is enhanced, but the device complexity increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidprocessing element array structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the processing element array into multiple channels with each channel containing a subset of processing elements. This segmentation allows the system to manage the complexity of a large number of processing elements by organizing them into structured, manageable units. Each channel can be independently controlled and scheduled, making the overall system more manageable while maintaining high processing capability through parallel operations across multiple channels.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12314843B2Neural network operation method and apparatus with mapping orders
Publication Date: 2025.05.27 SAMSUNG ELECTRONICS CO LTD
  • US12314843B2 patent drawing
  • US12314843B2 patent drawing
  • US12314843B2 patent drawing

AI summary

A neural network operation apparatus includes an input register to store an input feature map, a processing element array including a processing element to perform an operation based on the input feature map and a weight matrix, and a controller to map a portion of the input feature map and a portion of the weight matrix, both on which the operation is to be performed, to the processing element.