Neural Network Prefetching for Storage Class Memory
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Solution Overview
Problem
The memory hierarchy gap between DRAM and NAND flash memory results in high access time, requiring numerous computing machines to analyze large-scale data, leading to increased costs and inefficiencies in data placement and prefetching mechanisms, especially when using storage class memory to expand main storage capacity.
Innovation Solution
A data processing apparatus that splits block addresses into bit ranges, determines prediction accuracy for each range, and prefetches data based on this accuracy, using neural networks to predict future data access patterns and optimize cache management in storage class memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage class memory is used to expand main storage capacity, then storage capacity is increased, but access time increases due to the memory hierarchy gap
Solution Approach 1:
The system performs preliminary actions by predicting future data access patterns using neural networks and prefetching data from storage class memory to DRAM cache before it is actually needed. This advance preparation reduces the impact of the memory hierarchy gap by having data ready in faster memory when access is required.
Solution Approach 2:
The patent segments the prefetching process into multiple components: address pattern recognition, prediction accuracy determination for different bit ranges, and selective prefetching. This segmentation allows the system to optimize prefetching operations by treating different address patterns differently, improving overall access efficiency.
2Measurement precision
If neural networks are used to predict data access patterns, then prefetch accuracy is improved, but device complexity increases
Solution Approach 1:
The system divides the complex task of predicting entire block addresses into smaller sub-tasks by analyzing individual bit ranges separately. Each neural network focuses on predicting specific bit ranges (e.g., high-order bits, low-order bits) independently, which simplifies the overall system architecture while maintaining high prediction accuracy through coordinated analysis of all bit ranges.
Solution Approach 2:
Different prediction strategies and neural network configurations are applied to different bit ranges based on their specific characteristics. High-order bits may require different prediction approaches compared to low-order bits, allowing the system to optimize each local prediction task according to its specific requirements rather than using a uniform approach.
3Speed
If data is prefetched from storage class memory, then access speed is improved, but memory hierarchy overhead increases
Solution Approach 1:
The storage class memory subsystem performs self-service by autonomously managing the prefetching process based on predicted access patterns. The system automatically identifies which data to prefetch, when to prefetch it, and where to place it in the memory hierarchy, reducing the need for complex external control mechanisms and minimizing overhead.
Solution Approach 2:
The system implements feedback mechanisms where actual access patterns are monitored and used to refine prediction models. This continuous feedback loop allows the memory hierarchy to adapt to changing workloads and optimize prefetching decisions, reducing overhead by making increasingly accurate predictions that require less intervention.
Data Source
AI summary
An area for prefetching is determined while accommodating an increase in a block address space. A prediction model predicts prefetch addresses for each of bit ranges into which block addresses are split by using a plurality of neural networks assuming charge of the different bit ranges having performed machine learning on I/O trace data, a prediction accuracy determination section determines a size of an area for prefetching on the basis of addresses in the bit range for which prediction accuracy in prefetch is lower than a predetermined value, a predicted value determination section determines addresses of the area for prefetching on the basis of addresses in the bit range for which the prediction accuracy in the prefetch is equal to or higher than the predetermined value, and a prefetch issuance section caches data in the area for prefetching in a storage class memory from a NAND flash memory.