Neural Network Processing Device Hardware Integration
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Solution Overview
Problem
Existing neural network processing devices face challenges in hardware mounting due to complex architectures and large number of operations required for efficient image signal processing.
Innovation Solution
A neural network processing device is designed with a convolution part, batch adjustment part, and activation part, which perform convolution operations, adjust output deviations, and normalize signals using specific equations and quantization methods to facilitate efficient hardware integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex architectures and large number of operations are used for efficient image signal processing, then processing performance is improved, but hardware mounting difficulty increases
Solution Approach 1:
The patent applies parameter changes by normalizing learning parameters (weights and biases) to specific ranges (weights to [-1, 1] and biases to [-128, 127]) and transforming activation functions to output standardized ranges. This parameter standardization reduces hardware complexity while maintaining processing efficiency, as evidenced by the simplified quantization operations and reduced computational requirements in the hardware implementation.
Solution Approach 2:
The patent segments the neural network processing into distinct modular components: convolution layers, batch normalization layers, and activation layers. Each layer type is implemented as a separate hardware module with standardized interfaces, making the overall system easier to mount and maintain while preserving processing performance through organized functional decomposition.
2Measurement precision
If learning parameters are not normalized, then model accuracy is preserved, but quantization complexity and hardware implementation difficulty increase
Solution Approach 1:
The patent transforms learning parameters through normalization to fixed ranges that facilitate quantization. Weights are scaled to [-1, 1] and biases to [-128, 127], enabling efficient fixed-point arithmetic in hardware. The activation functions are also transformed to output standardized ranges, simplifying the quantization process while preserving model accuracy through careful parameter transformation.
Solution Approach 2:
The patent performs preliminary normalization of learning parameters during the model preparation phase, before hardware deployment. By pre-processing weights and biases to standardized ranges and pre-calculating scaling factors, the patent eliminates the need for complex runtime normalization operations in hardware, thereby simplifying manufacturing while maintaining accuracy.
3Productivity
If standard activation functions are used, then model performance is maintained, but output signal range variability increases hardware complexity
Solution Approach 1:
The patent modifies activation functions to produce standardized output ranges regardless of input variations. By transforming activation functions to consistently output values within specific ranges, the patent simplifies downstream processing and reduces hardware complexity in signal handling while preserving the essential non-linear transformation properties needed for model performance.
Data Source
AI summary
A neural network processing device includes: a convolution part which receives an input signal and a learning completion weight parameter, performs a convolution operation on the input signal and the learning completion weight parameter, and outputs a convolution signal that is a result value of the convolution operation; a batch adjustment which receives the convolution signal and a learning completion normalization parameter, and outputs an adjustment signal obtained by adjusting an output deviation of the convolution signal; and an activation part which converts the adjustment signal into an output signal based on an activation function.