Neural Network Processor Architecture with Parallel Instruction Units
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Solution Overview
Problem
Current CPU and GPU implementations of convolutional neural networks (CNNs) are inefficient due to their inability to fully adapt to the characteristics of CNNs, leading to lower computation efficiency and higher power consumption and cost.
Innovation Solution
A processor architecture comprising a memory controller group, on-chip bus, processor core array, instruction units, data transferring controller, buffer module, and computation module is proposed, which includes multiple computation units and flexible buffer management to optimize neural network operations, allowing for parallel execution and dynamic adaptation to CNN characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU or GPU is used to implement CNN, then general-purpose computing capability is provided, but computation efficiency is low and power consumption is high
Solution Approach 1:
The processor is divided into multiple processor cores, each containing independent instruction units and computation units. This segmentation allows parallel processing of different neural network operations simultaneously, improving computation efficiency while distributing power consumption across multiple smaller units rather than concentrating it in a single high-power GPU
Solution Approach 2:
The processor changes the operational parameters by providing multiple instruction units within each processor core that can execute different types of instructions (e.g., convolution, activation, pooling) simultaneously. This parameter change enables the system to adapt to different CNN operation types without switching between different hardware components, reducing overhead and improving efficiency
2Productivity
If multiple instruction units are provided in each processor core, then instruction processing capability is improved, but device complexity increases
Solution Approach 1:
Multiple instruction units within each processor core are designed to handle different types of neural network instructions (convolution, activation, pooling, etc.) using a unified architecture. This multi-functionality approach allows the same physical structure to perform multiple operations, improving instruction processing capability without proportionally increasing device complexity
Solution Approach 2:
The patent merges the instruction decoding and execution functionality into integrated instruction units within each processor core. By combining these functions that were previously separated in CPU/GPU architectures, the system achieves efficient instruction processing while maintaining a compact core structure
3Speed
If on-chip buffer is used for data storage, then access speed is improved, but on-chip area increases
Solution Approach 1:
The buffer module is strategically placed on-chip at locations where data access is most frequent (between external storage and computation units). This local buffering approach provides fast access for critical data paths while avoiding the need to expand buffer capacity across the entire chip, thus improving access speed without proportionally increasing total on-chip area
Data Source
AI summary
The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, a first instruction unit, a second instruction unit, an instruction distributing unit, a data transferring controller, a buffer module and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.