Neural Network Processor Array Bypass for Defective Cores
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Solution Overview
Problem
Neural network processor arrays face challenges in maintaining functionality when defective cores occur, as existing designs often require interruption or significant performance degradation due to the need to bypass or replace defective cores, which can disrupt the grid's location-sensitive operations and increase power consumption.
Innovation Solution
The implementation of a grid-based neural network processor system that allows for the bypassing of defective cores by providing connections between non-adjacent rows or columns, enabling transparent routing of messages past the defective core, thus maintaining seamless operation and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the neural network processor array uses a regular grid structure with adjacent core connections, then the routing is simple and power consumption is low, but the system cannot tolerate defective cores without interruption or performance degradation
Solution Approach 1:
The network is segmented into multiple routing paths between non-adjacent rows and columns, allowing messages to be divided and transmitted through alternative routes when defective cores are encountered, thereby providing defect tolerance without requiring complete system interruption
Solution Approach 2:
The patent extends the routing capability from two-dimensional adjacent connections to three-dimensional non-adjacent connections by adding vertical and horizontal bypass paths that connect non-adjacent rows and columns, enabling messages to route around defective cores in multiple dimensions
2Reliability
If the system implements bypass paths for defective cores, then defect tolerance is improved, but the routing complexity and power consumption increase
Solution Approach 1:
The patent implements selective bypass routing where only the minimum necessary paths are activated to route around defective cores rather than maintaining all possible bypass paths active, reducing power consumption while still providing defect tolerance when needed
Solution Approach 2:
The patent introduces intermediate routing nodes that act as mediators between non-adjacent rows and columns, allowing messages to be transferred through intermediate points rather than requiring direct long-range connections, thereby reducing the complexity and power consumption of the bypass network
3Productivity
If the system uses transparent routing to bypass defective cores, then operational continuity is maintained, but the network complexity increases
Solution Approach 1:
The patent designs the network interconnect to serve multiple functions: it handles both adjacent and non-adjacent core communications through the same infrastructure, allowing the system to maintain operational continuity for defective cores while also supporting normal adjacent routing without requiring separate dedicated bypass networks
Solution Approach 2:
The patent implements dynamic routing capabilities where the network can adaptively select between adjacent and non-adjacent paths based on the presence and location of defective cores, allowing the system to maintain operational continuity while managing routing complexity through intelligent path selection rather than fixed complex wiring
Data Source
AI summary
Defect resistant designs for location-sensitive neural network processor arrays are provided. In various embodiments, plurality of neural network processor cores are arrayed in a grid. The grid has a plurality of rows and a plurality of columns. A network interconnects at least those of the plurality of neural network processor cores that are adjacent within the grid. The network is adapted to bypass a defective core of the plurality of neural network processor cores by providing a connection between two non-adjacent rows or columns of the grid, and transparently routing messages between the two non-adjacent rows or columns, past the defective core.