Neural Network Processor with Flexible Buffer Pool
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Solution Overview
Problem
Current CPU and GPU implementations of convolutional neural networks (CNNs) fail to fully adapt to the characteristics of CNNs, leading to lower computation efficiency and higher power consumption and cost due to their inability to effectively handle the large computation requirements and bandwidth needs of these networks.
Innovation Solution
A processor architecture comprising a memory controller group, an on-chip bus, a processor core array with a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, and a computation module, which includes multiple computation units, is designed to optimize neural network operations by improving data management and parallel processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU or GPU is used to implement CNN, then the system can perform general-purpose computing, but computation efficiency is low and power consumption is high
Solution Approach 1:
The processor is divided into multiple computation units (CU0-CUN) that can independently execute neural network operations. Each computation unit contains dedicated functional blocks for convolution, activation, and pooling operations, enabling parallel processing of different neural network layers or batches, thereby improving computation efficiency while distributing power consumption across multiple units
Solution Approach 2:
A buffer pool is introduced as an intermediary component to store intermediate computation results and input data. This buffer pool acts as a mediator between data storage and computation units, reducing repeated memory access operations and enabling computation units to efficiently retrieve data without directly accessing external memory, thus improving computation efficiency and reducing power consumption
2Productivity
If CPU or GPU is used to implement CNN, then the system has high adaptability to different algorithms, but computation efficiency is low
Solution Approach 1:
The computation units are equipped with specialized functional blocks tailored for specific neural network operations. Each computation unit contains convolution functional blocks, activation functional blocks, and pooling functional blocks that are locally optimized for their respective functions, enabling efficient execution of CNN-specific operations while maintaining adaptability through configurable parameters
Solution Approach 2:
The processor employs a configurable architecture where computation units can be dynamically allocated and configured based on the specific neural network model being executed. The system can adapt the number and configuration of active computation units, buffer pool size, and data flow patterns to match the computational requirements of different CNN architectures, thereby achieving both high computation efficiency and adaptability
3Productivity
If traditional processor architecture is used, then the system has simple structure, but it cannot handle large computation requirements and bandwidth needs of CNN
Solution Approach 1:
Multiple functional blocks (convolution, activation, pooling) are merged within each computation unit to create an integrated processing element. This merging reduces the number of separate components needed, simplifies data flow paths, and enables efficient intra-unit communication, thereby improving computation efficiency without proportionally increasing overall system complexity
Solution Approach 2:
The processor employs a hierarchical nested structure where computation units are nested within the processor core array, buffer pools are nested within the data management subsystem, and functional blocks are nested within computation units. This nested organization allows each level to operate semi-independently while maintaining overall system coherence, managing complexity through hierarchical abstraction
Data Source
AI summary
The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer pool, a data reading scheduling unit and a computation module. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.