Neural Network Processor 1x1 Convolution Segmentation
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Solution Overview
Problem
Convolutional neural networks (CNNs) require extensive computational resources and energy, and implementing 1×1 convolutions using array convolution units in legacy neural network processors is inefficient.
Innovation Solution
The method involves a neural network processor with multiple building blocks that utilize N×N convolution units for expanding, grouping, and condensing operations, followed by non-grouped convolutions to efficiently process CNNs, reducing computational load and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 1×1 convolutions are implemented using array convolution units in legacy neural network processors, then the processor can support traditional CNN architectures, but the computational efficiency and energy consumption are significantly degraded
Solution Approach 1:
The patent segments the convolution operation into two distinct stages: grouped convolution for spatial feature extraction and 1×1 convolution for channel mixing. This segmentation allows each stage to use optimized hardware units appropriate for its specific function, with the 1×1 convolution unit specifically designed for efficient channel-wise operations rather than using general-purpose array convolution units.
Solution Approach 2:
The patent introduces an intermediary 1×1 convolution unit that acts as a bridge between the grouped convolution stage and the final output. This intermediary unit is specifically designed to handle channel mixing operations efficiently, serving as a specialized component that resolves the inefficiency of using general-purpose array units for 1×1 convolutions.
2Device complexity
If 1×1 convolutions are implemented using array convolution units, then the processor maintains hardware simplicity, but energy consumption increases significantly
Solution Approach 1:
The patent applies local quality by designing a specialized 1×1 convolution unit with architecture optimized specifically for channel mixing operations. This unit has different structural characteristics compared to general-purpose array convolution units, with features tailored to minimize energy consumption for 1×1 convolution operations while maintaining overall processor functionality.
Solution Approach 2:
The patent changes the architectural parameters of the convolution unit by introducing a dedicated 1×1 convolution unit with specific design characteristics optimized for its function. This parameter change includes optimizing the unit's internal structure, data flow, and computational approach to reduce energy consumption compared to using standard array convolution units for the same operation.
3Productivity
If grouped convolution is used to reduce computational load, then the number of operations decreases, but additional processing stages (splitting and combining) are required
Solution Approach 1:
The patent employs dynamic virtual grouping that can adapt to different input configurations and network requirements. The grouping mechanism is not fixed but can be dynamically adjusted based on the specific convolution operation being performed, allowing the system to optimize the balance between computational reduction and processing stage complexity for each operation.
Solution Approach 2:
The patent designs the grouped convolution mechanism to serve multiple functions: it reduces computational load through channel grouping, enables efficient 1×1 convolution operations, and provides a framework that can accommodate various convolution configurations. This multi-functionality reduces the need for separate specialized hardware for each operation type.
Data Source
AI summary
An integrated circuit with arrays of convolution units that include hardware convolution neural network units configured to perform efficient expansion process by parallelization. The integrated circuit includes multiple building blocks that include the arrays of convolution units, inputs, and outputs t.