Neural Network Processor Parallel Instruction Issue Module
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Solution Overview
Problem
Current neural network processors face inefficiencies in data processing due to sequential instruction execution and limited parallel processing capabilities, particularly in tasks like image processing for applications in computer vision, which hampers performance in areas such as face recognition, image classification, and semantic segmentation.
Innovation Solution
A neural network processor architecture that includes a convolution processing unit, a vector processing unit, and an instruction issue module, where the instruction issue module can issue multiple instructions in parallel to both units, enabling simultaneous processing of data and improving calculation efficiency by executing fine-grained instructions within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single-issue instructions are used in neural network processors, then device complexity is reduced, but productivity deteriorates due to sequential execution limitations
Solution Approach 1:
The instruction issue module is segmented into multiple independent issue lanes (first issue lane, second issue lane, third issue lane) that can independently issue instructions to different processing units simultaneously. This segmentation enables parallel instruction issuance without requiring complex centralized control logic, thus improving productivity while keeping individual lane complexity manageable.
Solution Approach 2:
The instruction issue module is designed with multi-functionality to handle different types of instructions (convolution instructions, vector instructions, matrix instructions) through a unified parallel issuing mechanism. The same issue lanes can dynamically issue different instruction types based on operational needs, avoiding the need for separate dedicated issue modules for each instruction type.
2Productivity
If multiple processing units are added to improve parallel processing capability, then productivity improves, but device complexity increases
Solution Approach 1:
The processing units are segmented into specialized functional units (convolution processing unit, vector processing unit, matrix processing unit), each optimized for specific operations. This segmentation allows parallel execution of different operation types without requiring a single complex general-purpose unit, improving productivity while keeping each unit's internal complexity manageable.
Solution Approach 2:
The instruction issue module acts as an intermediary that manages the complexity of coordinating multiple processing units. It receives high-level operational requirements and translates them into specific instruction sequences for the appropriate processing units, shielding the upper-level control logic from the complexity of direct unit coordination.
3Productivity
If fine-grained instructions are executed within a single clock cycle, then productivity improves, but the difficulty of detecting and measuring increases
Solution Approach 1:
The instruction issue module dynamically changes the parameter of instruction granularity by issuing different numbers of instruction bits per clock cycle based on the specific operational requirements. For fine-grained operations, it issues smaller instruction units that can be completed within a single clock cycle, while for coarser operations, it issues larger instruction bundles, thus adapting execution speed to task requirements without requiring complex real-time detection mechanisms.
Data Source
AI summary
The embodiments of the disclosure provide a neural network processor, a chip and an electronic device. The neural network processor includes a convolution processing unit, a vector processing unit, and an instruction issue module. The convolution processing unit and the vector processing unit are both connected to the instruction issue module. The instruction issue module is configured to issue a plurality of instructions to the convolution processing unit and the vector processing unit in parallel. The embodiments of the application can improve the efficiency of the neural network processor processing data.