Neural Network Processor Segmentation for Computation Efficiency
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Solution Overview
Problem
Current CPU and GPU implementations of convolutional neural networks (CNNs) are inefficient due to their inability to fully adapt to the characteristics of CNNs, leading to lower computation efficiency and higher power consumption and cost.
Innovation Solution
A processor design comprising a memory controller group, on-chip bus, processor core array, convolution operation units, and a hybrid computation unit, optimized for neural network operations with a buffer pool and multi-channeled data scheduling units to enhance parallel processing and adapt to CNN characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU or GPU is used to implement CNN, then the system can process neural network operations, but computation efficiency is low and power consumption is high
Solution Approach 1:
The processor is divided into multiple independent computation units including convolution operation units and hybrid computation units. Each unit can independently process different parts of the neural network computation, enabling parallel execution and improving overall computation efficiency while reducing the power consumption per unit of computation.
Solution Approach 2:
The patent introduces a specialized neural network processor architecture that operates in a different computational dimension compared to general-purpose CPUs or GPUs. By designing dedicated computation units for specific neural network operations (convolution, hybrid computation), the system achieves higher efficiency in the computational domain specific to neural networks.
2Productivity
If general-purpose CPU or GPU is used, then the system has high versatility, but it fails to adapt to CNN characteristics leading to lower computation efficiency
Solution Approach 1:
Different computation units are designed with specialized structures optimized for specific neural network operations. The convolution operation units are optimized for convolution computations, while hybrid computation units handle other operations. This local optimization allows each unit to efficiently process its designated operation type while maintaining overall system versatility.
Solution Approach 2:
The processor incorporates multiple types of computation units (convolution operation units, hybrid computation units) that can handle different neural network operations. This multi-functional design enables the system to adapt to various CNN architectures and operations while maintaining high computation efficiency for each specific operation type.
3Speed
If more computation resources are allocated to handle neural network operations, then computation speed improves, but device complexity increases
Solution Approach 1:
The processor architecture is segmented into multiple independent computation units, each with a relatively simple structure optimized for specific operations. This segmentation allows the system to achieve high processing speed through parallel execution while keeping individual unit complexity manageable.
Solution Approach 2:
A buffer module serves as an intermediary between the multiple computation units and the external memory system. This buffer module manages data flow and coordination between units, enabling high-speed parallel computation without requiring complex inter-unit communication infrastructure.
Data Source
AI summary
The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer module, a convolution operation unit and a hybrid computation unit. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.