Neural Network Operation Apparatus Reduction Logic
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Solution Overview
Problem
Existing neural network accelerators lack efficient support for reduction operations on input feature maps with large spatial dimensions, leading to high computational overhead and inefficiency.
Innovation Solution
A neural network operation apparatus with an internal storage, arithmetic logical unit (ALU), adder, multiplexers, and a controller, which generates control signals to perform reduction operations efficiently by separating operations into branches and using phase signals to manage data flow and quantization, allowing for reduced overhead and faster processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate core is implemented to support reduction operations, then the neural network operation capability is improved, but the device complexity and computational overhead increase significantly
Solution Approach 1:
The patent merges the reduction operation functionality into the existing convolution accelerator core by integrating a reduction device that shares computational resources (ALU, adders, memory) with the main convolution processing pipeline, eliminating the need for a separate dedicated core and reducing overall device complexity
Solution Approach 2:
The ALU and adder resources are designed to serve dual purposes: performing convolution operations during normal processing and performing reduction operations when triggered by control signals, allowing the same hardware to handle multiple neural network operations efficiently
2Manufacturing precision
If all values of two-dimensional feature maps are read for each output pixel to process large spatial dimension data, then the processing completeness is improved, but the processing time and computational load increase
Solution Approach 1:
The patent segments the processing into two distinct paths: a main processing path that handles convolution operations for most output pixels, and a reduction processing path that handles the aggregation of feature map values. This segmentation allows parallel processing and avoids reading all feature map values sequentially for each pixel
Solution Approach 2:
The reduction device acts as an intermediary component that receives feature map values and aggregates them through dedicated reduction operations (sum, max, avg), separating the aggregation function from the main convolution processing and enabling efficient handling of large spatial dimensions
3Device complexity
If typical accelerators are used without dedicated reduction support, then the device simplicity is maintained, but the reduction operation efficiency deteriorates
Solution Approach 1:
The patent implements dynamic resource allocation where the ALU and adder units can switch between convolution and reduction operations based on control signals. The system dynamically activates reduction functionality only when needed, maintaining simplicity during normal operation while enabling efficient reduction processing when required
Data Source
AI summary
A neural network operation apparatus and method are provided. The neural network operation apparatus includes an internal storage configured to store data to perform a neural network operation, an arithmetic logical unit (ALU) configured to perform an operation between the stored data and main data based on an operation control signal, an adder configured to add an output of the ALU and an output of a first multiplexer, wherein the first multiplexer is configured to output one of an output of the adder and the output of the ALU based on a reset signal, a second multiplexer configured to output one of the main data and a quantization result of the stored data based on a phase signal, and a controller configured to control the ALU, the first multiplexer, and the second multiplexer based on the operation control signal, the reset signal, and the phase signal.