Neural Network Skip Connection Memory Reduction via Time Offset

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Solution Overview

Problem

Existing neural networks with skip connections face challenges in achieving increased performance without synchronizing parallel pathways, requiring significant memory resources and being memory-hungry, especially in complex networks with multiple layers and skip connections.

Innovation Solution

Implementing a memory-efficient neural network system that processes data through primary and secondary flow paths with adjustable time offsets, eliminating the need for synchronization by allowing parallel pathways to operate with different delays, thereby reducing memory requirements and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronization is implemented in skip connections to ensure features from the same frame arrive at the summation point simultaneously, then the accuracy and reliability of the neural network is improved, but the memory requirements and device complexity increase significantly

Engineering Contradiction:
ImproveaccuracyVSAvoidmemory requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the synchronization mechanism from the skip connection pathway by introducing a separate synchronization layer. This allows the main data flow to proceed without requiring complex memory buffers for synchronization, while still achieving the desired temporal alignment at the summation point through the extracted sync layer.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

A synchronization layer is introduced as an intermediary component between the parallel pathways and the summation point. This mediator handles the temporal alignment function separately, allowing the main pathways to operate independently without direct memory resource consumption for synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If longer skip connection paths are implemented to maintain synchronization, then the performance improvement from skip connections is achieved, but the memory bandwidth requirements and on-chip memory needs increase

Engineering Contradiction:
ImproveperformanceVSAvoidmemory bandwidth
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The synchronization function is extracted from the data pathway itself and placed in a dedicated synchronization layer. This extraction allows skip connections to maintain their performance benefits without requiring proportional increases in memory bandwidth, as the sync layer handles temporal alignment independently.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system is segmented into distinct functional layers: the data processing pathways and the synchronization layer. This segmentation allows independent optimization of each function, enabling performance improvement through skip connections without proportionally increasing memory bandwidth requirements.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If multiple skip connections with varying complexity are provided in deep networks, then the network can handle complex processing tasks, but the difficulty of achieving synchronization and managing memory resources increases

Engineering Contradiction:
Improvenetwork capabilityVSAvoidsynchronization complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The synchronization layer serves as a universal mechanism that handles temporal alignment for all skip connections regardless of their complexity or position in the network. This multi-functional approach allows deep networks with varying skip connection configurations to maintain synchronization without managing individual complexity for each connection path.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240378055A1Methods and system for improved processing of sequential data in a neural network
Publication Date: 2024.11.14 BRAINCHIP INC
  • US20240378055A1 patent drawing
  • US20240378055A1 patent drawing
  • US20240378055A1 patent drawing

AI summary

Disclosed is a system that includes a processor configured to process data in a neural network and a memory associated with a primary flow path and at least one secondary flow path within the neural network. The primary flow path comprises one or more primary operators to process the data and the at least one secondary flow path is configured to pass the data to a combining operator by skipping the processing of the data over the primary flow path. The processor is configured to provide the primary flow path and the at least one secondary flow path with a primary sequence of data and a secondary sequence of data respectively such that the secondary sequence of data being time offset from the processed primary sequence of data.