Neural Network Sub-Network Division for Neuromorphic Core Memory
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Solution Overview
Problem
Efficient processing of large amounts of input data in real-time using memory-oriented neural networks is hindered by the physical size of the core memory, making it difficult to implement neural networks with thousands or tens of thousands of neurons, leading to energy expenditure and latency issues.
Innovation Solution
Divide the neural network into sub-networks based on the size of the core memory, initialize hyper-parameters for each sub-network, and train them separately to reduce the number of inputs and improve processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the neural network is implemented using a core memory of fixed size, then the device structure is simple, but the number of neurons that can be implemented is limited
Solution Approach 1:
The neural network is divided into multiple sub-networks, each mapped to a separate core memory. This segmentation allows the system to handle large-scale neural networks by distributing them across multiple smaller, manageable units, thereby overcoming the limitation of a single fixed-size core memory while maintaining structural simplicity.
Solution Approach 2:
The patent transitions from a single-core memory architecture to a multi-core memory architecture, adding the dimension of parallel processing capacity. This dimensional expansion enables the system to scale the number of neurons beyond what a single core can accommodate, effectively resolving the contradiction between structural simplicity and neural network capacity.
2Speed
If the neural network processes large amounts of input data in real-time, then the processing speed is high, but the power consumption increases
Solution Approach 1:
By segmenting the neural network into sub-networks distributed across multiple cores, the system can process large amounts of data in parallel. Each core handles a portion of the computational load independently, achieving high processing speed while distributing power consumption across multiple units rather than concentrating it in a single overloaded core.
Solution Approach 2:
Instead of requiring a single core to process all input data simultaneously (excessive action), the system distributes the processing workload across multiple cores (partial action). This approach enables real-time processing of large datasets by utilizing the collective capacity of multiple cores, thereby achieving high speed without proportional increases in overall power consumption.
3Productivity
If the neural network uses a memory-oriented architecture, then the information processing capability is improved, but the latency increases
Solution Approach 1:
The memory-oriented architecture is segmented into multiple independent cores, each capable of processing data simultaneously. This segmentation reduces latency by distributing memory access operations across multiple cores rather than having a single core sequentially access memory for the entire neural network, thereby improving information processing capability while reducing time loss.
Solution Approach 2:
Multiple cores continue processing operations simultaneously without waiting for sequential memory accesses to complete. This parallel continuity of useful action eliminates the latency bottleneck inherent in sequential memory-oriented processing, allowing the system to maintain high information processing capability while minimizing time loss through concurrent operations.
Data Source
AI summary
A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.