Neural Network Circuit Synapse Area Reduction

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Solution Overview

Problem

Conventional neural network circuits implementing the pulse timing model face an issue with increased circuit area due to the number of elements required, particularly in the synapse circuit, which hampers efficient information processing and learning operations.

Innovation Solution

A learning method for neural network circuits is developed, utilizing a configuration with fewer elements by incorporating a synapse circuit with a variable resistance element and a neuron circuit that generates bipolar sawtooth or mexican-hat pulse voltages, allowing for efficient learning operations using pulse timings. The synapse circuit includes a variable resistance element with a semiconductive layer, a ferroelectric layer, and control electrode, where the resistance value changes based on electric potential differences, enabling reduced circuit area and simplified configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the pulse timing model is used to represent information using every individual pulse, then information processing speed is improved, but the circuit area of the neural network circuit increases

Engineering Contradiction:
Improveinformation processing speedVSAvoidcircuit area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The patent merges the pulse generation function and the timing comparison function into a single integrated circuit element. The waveform generating circuit produces both the reference waveform and the pulse signal, eliminating the need for separate pulse generation circuits in each neuron. This integration reduces the overall circuit area while maintaining the ability to process pulse timing information at high speed.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The synapse circuit is designed to perform multiple functions: it generates the reference waveform, compares it with the input pulse signal, detects timing differences, and modulates synaptic strength. This multi-functionality reduces the number of separate circuits needed, thereby reducing the total circuit area while preserving high-speed pulse timing processing capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a conventional synapse circuit configuration is used, then learning operations can be performed, but the number of elements increases leading to larger circuit area

Engineering Contradiction:
Improvelearning operation capabilityVSAvoidnumber of elements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the learning function and the pulse processing function into a single synapse circuit. The variable resistance element directly modulates based on the timing comparison between reference and input pulses, integrating learning updates with signal processing. This eliminates the need for separate learning circuits and reduces the total number of elements required for learning operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The synapse circuit performs self-modulation of its resistance value based on the timing relationship between reference and input pulses. The learning update is automatically generated through the intrinsic operation of the circuit without requiring external control signals or separate learning algorithms, reducing the number of external elements needed while maintaining full learning capability.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the implementation of learning operations using pulse timings with a reduced number of elements, enhancing processing efficiency and reducing the circuit area, thereby overcoming the limitations of conventional neural network circuits.

Implementation Method 1

a control electrode formed on a main surface of the semiconductive layer via a ferroelectric layer, and changes a resistance value between the first electrode and the second electrode in response to an electric potential difference between the first electrode and the control electrode

Methodology Applied
Scientific EffectFerroelectric effect: Ferrofluid

Data Source

PatentUS8965821B2Learning method of neural network circuit
Publication Date: 2015.02.24 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US8965821B2 patent drawing
  • US8965821B2 patent drawing
  • US8965821B2 patent drawing

AI summary

A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a predetermined pulse voltage, and a first input signal has a waveform of the predetermined pulse voltage. For a period having a predetermined duration of the predetermined pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element, the first input signal is permitted to be input to the control electrode of the variable resistance element, to change the resistance value of the variable resistance element due to an electric potential difference generated between the first electrode and the control electrode which occurs depending on an input timing of the first input signal with respect to the period during which the first input signal is permitted to be input to the control electrode.