Neural Network Transistor Modeling for Fast Simulation
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Solution Overview
Problem
Circuit simulation is computationally intensive, with existing models either requiring high expertise for development or exhibiting high simulation turnaround times due to large look-up tables, limiting their effectiveness for emerging devices and large-scale circuits.
Innovation Solution
The development of compact neural network-based models for transistors that automatically adjust hyperparameters for faster simulation turnaround times and capture process variations, using a method that initializes and trains neural networks to match transistor output state values and derivatives, and re-targets models to fit electronic targets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional physics-based models or look-up-table-based methods are used for transistor modeling, then model accuracy can be maintained, but simulation turnaround time increases significantly
Solution Approach 1:
The patent transforms the transistor modeling approach by changing the mathematical parameters from traditional physics-based equations to neural network parameters (weights and biases). This parameter transformation enables the model to achieve both high accuracy and fast simulation speed, as the neural network parameters can be optimized to fit device characteristics while maintaining compact representation suitable for processor cache storage
Solution Approach 2:
The patent substitutes the traditional physics-based computational mechanism with a neural network-based mechanism. Instead of solving complex physics equations or searching large look-up tables, the system uses neural network forward propagation with optimized weights and biases, replacing the computational mechanics with a more efficient mathematical transformation that runs faster while maintaining accuracy
2Measurement precision
If large look-up tables are used to improve model accuracy, then transistor behavior can be captured precisely, but device complexity and memory requirements increase
Solution Approach 1:
The patent extracts only the essential parameters needed for accurate transistor modeling by training a neural network on device data. Instead of storing complete look-up tables, the system extracts and stores only the critical weights and biases that capture the essential transistor behavior, significantly reducing model complexity and memory requirements while maintaining accuracy
Solution Approach 2:
The patent inverts the traditional approach by not directly storing device characteristics in look-up tables, but rather training a neural network to learn these characteristics. The model structure is inverted from data-driven storage to learning-driven computation, where the neural network learns the underlying patterns and represents them compactly through weights and biases
3Productivity
If existing transistor models are used, then simulation can proceed, but model development requires high expertise and is not adaptable to emerging devices
Solution Approach 1:
The patent implements self-service by enabling automated neural network training and hyperparameter optimization for transistor modeling. The system automatically trains the model on device data, optimizes hyperparameters through grid search or random search, and generates the final model without requiring expert manual intervention, making the process accessible to users without specialized modeling expertise
Solution Approach 2:
The patent creates a universal modeling framework that can adapt to different transistor types and emerging devices. The same neural network architecture and training process can be applied to various device types (FinFETs, nanosheet FETs, etc.) by simply changing the training data, making the methodology universally applicable across current and future device technologies
Data Source
AI summary
A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.