Neural Network Processor Window Expander Circuit

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Solution Overview

Problem

Current neural network architectures struggle to efficiently compute both Convolutional Neural Networks (CNNs) and Recurrent Neural Networks (RNNs) simultaneously, often specializing in one type and compromising on performance for the other, while also facing challenges with real-time latency requirements.

Innovation Solution

A neural network processor is designed with a window expander circuit that expands input data to increase utilization of multiplier circuits, leveraging parallelism between output activations in CNNs and using a CNN-aware instruction set architecture to perform efficient matrix-matrix multiplication, allowing for high throughput at low latency for both CNNs and RNNs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If neural network processor specializes in one type of network (CNN or RNN), then performance for that type is improved, but performance for the other type deteriorates

Engineering Contradiction:
Improveprocessing performanceVSAvoidnetwork type compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal neural network processor that can efficiently handle both CNN and RNN operations through a unified architecture. The window expander circuit and multiplier circuits are designed to support multiple network types, allowing the same hardware to perform both convolutional and recurrent operations without specialization, thus achieving high productivity for both network types simultaneously

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If input data is expanded to increase multiplier circuit utilization, then processing throughput is improved, but computational complexity increases

Engineering Contradiction:
Improveprocessing throughputVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The window expander circuit divides the input data into multiple segments and processes them through parallel multiplier circuits. By segmenting the data processing task and distributing it across multiple multiplier circuits, the system achieves high throughput without requiring a single overly complex circuit, thus balancing productivity gains with manageable device complexity

Inventive Principle:
Principle #1Segmentation

3Loss of time

If real-time processing is implemented to meet latency requirements, then response time is improved, but processing accuracy may deteriorate

Engineering Contradiction:
Improveprocessing latencyVSAvoidcomputational accuracy
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The window expander circuit performs preliminary data expansion and preparation before the main computation occurs. By pre-processing the input data in the window expander, the system reduces the computational burden during the critical real-time processing phase, enabling both low latency and high accuracy to be achieved simultaneously through staged processing

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11151445B2Neural network processor with a window expander circuit
Publication Date: 2021.10.19 MICROSOFT TECHNOLOGY LICENSING LLC
  • US11151445B2 patent drawing
  • US11151445B2 patent drawing
  • US11151445B2 patent drawing

AI summary

Neural network processors including a window expander circuit and related methods are provided. The window expander circuit may include a first logic circuit configured to store a set of data elements, corresponding to at least a subset of the input data, into a Q number of logical memories, where each of a P number of data elements of the set of the data elements is stored in each of the Q number of logical memories. The window expander circuit may further include a second logic circuit configured to receive the first set of data elements and additional data elements corresponding to the at least the subset of the input data from the Q number of logical memories and expand the at least the subset of the input data until the at least the subset of the input data is expanded based on a predetermined factor.