Neural Network Parallel Processing Circuits With Compression Mapping
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Solution Overview
Problem
Existing neural network processing systems face challenges with high power consumption and computation efficiency due to the reliance on CPU or GPU for operations, which are not optimized for the specific requirements of neural network computations.
Innovation Solution
An integrated circuit chip device is designed with a primary processing circuit and multiple basic processing circuits arranged in an array, where the basic processing circuits include compression mapping circuits to compress data before operations, reducing the need for extensive computation and data transmission, thereby lowering power consumption and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If CPU or GPU is used to implement neural network operations, then the system can perform general-purpose computing, but power consumption and computation resources are excessively high
Solution Approach 1:
The processing system is segmented into a primary processing circuit and multiple basic processing circuits arranged in an array. Each basic processing circuit is connected to adjacent circuits, creating a distributed processing architecture that divides the computational workload and reduces the energy burden on any single processing unit while maintaining high computation efficiency through parallel operations.
Solution Approach 2:
A compression mapping circuit is introduced as an intermediary component that compresses data before it enters the main processing pipeline. This compression mechanism reduces the volume of data requiring computation and transmission, thereby lowering power consumption without significantly compromising the overall computation efficiency of the neural network operations.
2Productivity
If data is transmitted extensively between processing units, then computation can be performed, but data transmission resources and power consumption increase
Solution Approach 1:
The compression mapping circuit performs data compression in advance, before the data is transmitted to and processed by the basic processing circuits. This preliminary compression action reduces the data volume that needs to be transmitted across the processing array, thereby maintaining processing speed while significantly reducing the energy consumed during data transmission.
3Use of energy by moving object
If compression mapping circuit is used to compress data, then power consumption and computation resources are reduced, but device complexity increases
Solution Approach 1:
The compression mapping circuit is integrated within the basic processing circuits themselves, merging the compression function with the processing units. This integration approach reduces device complexity by eliminating the need for separate, dedicated compression hardware while still achieving the power consumption benefits of data compression.
Data Source
AI summary
The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.