Neural Network Pipeline With Multifunction Units for Low-Latency Throughput
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Solution Overview
Problem
Neural networks are expensive to deploy using general-purpose CPUs or GPUs, and GPUs provide increased throughput but suffer from poor latency in processing complex tasks like reading comprehension, language translation, and speech recognition.
Innovation Solution
A processor pipeline architecture that includes a matrix vector unit and multifunction units, where instructions are decoded and mapped for processing by specific units based on their types, allowing for efficient processing of neural network operations across multiple nodes, such as FPGAs, to leverage parallelism and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose CPUs are used to deploy neural networks, then versatility is maintained, but processing speed and throughput deteriorate
Solution Approach 1:
The system segments neural network processing into distinct functional units: matrix vector units for parallel computation, multifunction units for different operation types, and specialized decoding units. This segmentation enables each unit to be optimized for specific tasks while maintaining overall system versatility through programmable control.
Solution Approach 2:
The patent implements multifunction units that can perform multiple neural network operations (matrix multiplication, convolution, activation functions) within a single hardware structure. The decoder can interpret different instruction types to route operations to appropriate units, providing universal neural network processing capability while achieving high throughput through hardware acceleration.
2Productivity
If GPUs are used to increase throughput, then processing capacity improves, but latency deteriorates
Solution Approach 1:
The system pre-loads neural network weights and parameters into on-chip memory before processing begins. The pipeline architecture is pre-configured with multiple stages that can process data in parallel, reducing the time required for actual inference or training operations while maintaining high throughput capacity.
Solution Approach 2:
The patent implements a continuous pipeline architecture where multiple operations overlap in time. While one matrix vector unit processes data, another performs activation functions, and a third prepares output. This continuous operation eliminates idle time between operations, reducing latency while maintaining high throughput through parallel processing stages.
3Productivity
If parallelism is exploited across multiple nodes to reduce training time, then processing speed improves, but system complexity increases
Solution Approach 1:
The patent combines multiple processing functions into integrated units on each node. Matrix vector units, multifunction units, and memory are merged into a cohesive system that can operate independently yet coordinate with other nodes. This merging reduces communication overhead and synchronization complexity while enabling parallel training across hundreds of thousands of nodes.
Solution Approach 2:
The system employs dynamic instruction decoding and routing that adapts to different neural network operations. The decoder dynamically determines which multifunction unit should handle each operation based on the instruction type, allowing flexible parallel execution across nodes without requiring complex static scheduling mechanisms.
Data Source
AI summary
Processors and methods for neural network processing are provided. A method in a processor including a pipeline having a matrix vector unit (MVU), a first multifunction unit connected to receive an input from the MVU, a second multifunction unit connected to receive an output from the first multifunction unit, and a third multifunction unit connected to receive an output from the second multifunction unit is provided. The method includes decoding instructions including a first type of instruction for processing by only the MVU and a second type of instruction for processing by only one of the multifunction units. The method includes mapping a first instruction for processing by the matrix vector unit or to any one of the first multifunction unit, the second multifunction unit, or the third multifunction unit depending on whether the first instruction is the first type of instruction or the second type of instruction.