Neural Processor Clock Scaling for Voltage Drop Stability
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Solution Overview
Problem
Neural network processors experience voltage drops below the minimum operating voltage range due to sudden increases in power consumption during state transitions, leading to incorrect operation results and potential abnormalities.
Innovation Solution
Adjust the first clock frequency of the clock signal to generate an output clock signal with a lower frequency, reducing the power consumption change rate and maintaining the neural network processor's voltage within the operating range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the neural network processor operates at high power consumption, then the processing capability is improved, but the voltage drops below the minimum operating voltage range
Solution Approach 1:
The patent applies preliminary action by lowering the clock frequency before the processor enters high-power consumption mode. The clock signal generating module adjusts the clock frequency in advance based on predicted power consumption patterns, ensuring that when the processor transitions to high-power operation, the voltage has already been stabilized by the power management circuit, preventing voltage drops below the minimum operating threshold
Solution Approach 2:
The patent implements dynamics by making the clock frequency adjustable and adaptive. The clock signal generating module dynamically changes the clock frequency based on the operational state and power consumption characteristics of the neural network processor. This allows the system to optimize between processing capability and voltage stability by adjusting the clock frequency in real-time according to power consumption levels
2Reliability
If the clock frequency is reduced to lower power consumption change rate, then voltage stability is improved, but processing speed decreases
Solution Approach 1:
The patent applies dynamics by implementing a variable clock frequency system that adapts to different operational conditions. The clock signal generating module adjusts the clock frequency based on the processor's power consumption characteristics and operational state, allowing the system to optimize between voltage stability and processing speed dynamically rather than using a fixed frequency
Solution Approach 2:
The patent implements parameter changes by modifying the clock frequency parameter based on power consumption patterns. The system changes the clock frequency parameter in response to detected or predicted power consumption levels, allowing the processor to operate at lower frequencies during high-power consumption periods to maintain voltage stability, and at higher frequencies during lower-power periods to maximize processing speed
Data Source
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AI summary
Disclosed are an instruction execution method and apparatus, and an instruction generation method and apparatus, relating to the technical field of integrated circuits. The instruction execution apparatus comprises: a clock signal generation module, used for adjusting a first clock frequency of a first clock signal generated by a clock signal source, so as to generate an output clock signal, the clock frequency of the output clock signal comprising a second clock frequency, and the second clock frequency being lower than the first clock frequency; and a hardware computation module, used for determining an operation instruction and executing the operation instruction according to the output clock signal. The embodiments of the present disclosure can reduce the rate of change of power consumption of the hardware computation module. Therefore, the amplitude of a voltage drop of a neural network processor is small, and it is ensured that the voltage of the neural network processor is always in a working voltage range, which may not only ensure the accuracy of operation results, but also avoid the occurrence of abnormalities in the neural network processor.