Neural Processor Dynamic Data Communication Mode Selection
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Solution Overview
Problem
Neural processing units face timing issues due to component operation errors and transmission delays, which can occur even in perfectly designed chips, especially as components deteriorate over time, leading to unpredictable performance.
Innovation Solution
A neural processor and processing device that can dynamically select between synchronous and asynchronous data communication modes based on the operating frequencies of its components, using a data communication mode determiner to adjust the communication mode according to test results and operational conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous data communication mode is used, then data communication reliability is improved, but timing issues occur due to component operation errors and transmission delays
Solution Approach 1:
The patent implements dynamic switching between synchronous and asynchronous data communication modes based on real-time timing status. The determination unit monitors timing issues and dynamically selects the appropriate communication mode, transforming a static system into a dynamic one that adapts to changing conditions to resolve the contradiction between reliability and timing performance.
Solution Approach 2:
The patent changes the communication mode parameter from fixed synchronous to variable (synchronous/asynchronous) based on timing status. By adjusting this parameter dynamically, the system can switch between modes to avoid timing issues while maintaining data communication reliability, effectively resolving the technical contradiction.
2Loss of time
If asynchronous data communication mode is used, then timing issues are avoided, but data communication reliability deteriorates
Solution Approach 1:
The system dynamically switches between asynchronous and synchronous modes based on timing status. When timing issues are detected, it transitions to asynchronous mode to avoid them; when timing is stable, it switches back to synchronous mode to maintain high reliability, thus resolving the contradiction between avoiding timing issues and maintaining reliability.
Solution Approach 2:
The determination unit continuously monitors timing status and provides feedback to the mode selection mechanism. This feedback loop enables the system to adjust communication mode based on actual timing performance, ensuring reliability is maintained while avoiding timing issues through intelligent decision-making.
3Ease of manufacture
If fixed chip design is used, then manufacturing complexity is reduced, but adaptability to timing issues deteriorates
Solution Approach 1:
The patent adds dynamic mode switching capability to a fixed chip design without requiring redesign. The determination unit and mode switching mechanism enable the chip to adapt to timing issues occurring during operation, maintaining manufacturing simplicity while gaining operational adaptability.
Solution Approach 2:
The chip is pre-designed with the capability to detect timing issues and switch modes, but the actual mode selection is determined in advance based on timing status before data communication occurs. This preliminary determination allows the fixed design to handle variable timing conditions without requiring complex adaptive hardware.
Data Source
AI summary
A neural processing device is provided, which includes a first block that operates at a first operating frequency and at a second operating frequency different from the first operating frequency, a second block operates at the first operating frequency, and a data communication mode determiner that controls data communication between the first block and the second block, and determines a first data communication mode for a first interface between the first block and the second block.