Neural Network Processor Architecture for Self-Learning Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Convolutional deep learning processes in artificial neural networks face high costs due to the need for large numbers of labeled samples and performance bottlenecks in existing devices like general-purpose processors and GPUs, which hinder efficient multilayer neural network operations.
Innovation Solution
A neural network acceleration processor with a master computation module and slave computation modules connected via an interconnection unit, where each slave module stores and multiplies input vectors with column weight vectors, generating and combining results to optimize self-taught learning algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general-purpose processor is used for self-taught learning algorithms, then versatility is improved, but operational performance deteriorates
Solution Approach 1:
The processor is divided into multiple computation modules (master computation module and slave computation modules) that can independently execute different operations. This segmentation allows the system to achieve high performance for specific neural network operations while maintaining versatility through configurable module assignments.
Solution Approach 2:
The computation modules can be dynamically configured and assigned different functions based on the specific algorithm being executed. The master computation module can coordinate with multiple slave modules in different configurations, allowing the same hardware to adapt to various self-taught learning algorithms and neural network architectures.
2Productivity
If multiple general-purpose processors execute concurrently, then operational performance is improved, but device complexity increases due to intercommunication bottlenecks
Solution Approach 1:
Multiple computation modules are merged into a single integrated processor device with a unified architecture. The master computation module and slave computation modules work together as a coordinated system, eliminating the need for complex inter-processor communication protocols and reducing overall system complexity while maintaining high computational throughput.
3Productivity
If a GPU with small on-chip caching is used, then operational performance is improved, but power consumption increases due to repeated off-chip data movement
Solution Approach 1:
Weight values are pre-loaded and cached in on-chip memory before computation begins. The slave computation modules have direct access to these pre-cached weight values, eliminating the need for repeated off-chip data movements during the computation process and significantly reducing power consumption.
Solution Approach 2:
An on-chip caching mechanism acts as an intermediary between the computation modules and off-chip memory. This intermediate storage layer holds frequently accessed weight values, allowing computation modules to access data quickly without repeatedly accessing external memory, thereby reducing both computational bottlenecks and power consumption.
Data Source
AI summary
Aspects for self-learning operations of an artificial neural network are described herein. The aspects may include a master computation module configured to transmit an input vector via an interconnection unit and one or more slave computation modules connected to the master computation module via the interconnection unit. Each of the one or more slave computation modules may be configured to respectively store a column weight vector of a weight matrix and multiply the input vector with the column weight vector to generate a first multiplication result. The interconnection unit may be configured to combine the one or more first multiplication results into a first multiplication vector and transmit the first multiplication vector to the master computation module.