Neural Network Parameter Quantization for FPGA Base Calling
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Solution Overview
Problem
Deploying deep Convolution Neural Networks (CNNs) on portable and embedded systems is challenging due to large data volume, intensive computation, varying algorithm structures, and frequent memory accesses, which affects the efficiency and performance of hardware accelerators like FPGAs.
Innovation Solution
Implementing a neural network parameter quantization method using configurable processors, such as FPGAs, to optimize CNN inference by minimizing data communication and maximizing resource utilization through efficient dataflow and hardware architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If deep CNNs are deployed on portable and embedded systems, then computation capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the CNN computation into discrete processing elements (PEs) arranged in a grid architecture, where each PE handles specific convolution operations. This segmentation allows the complex CNN to be broken down into manageable, parallel units that can be efficiently implemented on FPGAs, reducing overall device complexity while maintaining computation capability.
Solution Approach 2:
The patent introduces a temporal dimension by implementing multi-cycle convolution operations, where computations are distributed across multiple clock cycles. This dimensional transformation allows complex operations to be performed sequentially in time rather than requiring all resources simultaneously, thereby reducing spatial device complexity while preserving computational power.
2Productivity
If convolution operations are accelerated with high parallelism, then productivity is improved, but use of energy increases
Solution Approach 1:
The patent implements periodic computation by distributing convolution operations across multiple clock cycles, where each PE performs computations in alternating phases. This periodic action allows energy-consuming operations to be spread out in time rather than concentrated in a single high-power burst, maintaining productivity while reducing peak energy consumption.
Solution Approach 2:
The patent ensures continuous useful action by keeping PEs actively engaged in computation across multiple cycles without idle periods. Each PE continuously processes data through the multi-cycle convolution pipeline, maintaining high productivity while avoiding the energy waste associated with frequent on/off switching and idle states.
3Loss of time
If data communication is minimized in hardware architecture, then loss of time is reduced, but device complexity increases
Solution Approach 1:
The patent merges the data storage and processing functions by implementing on-chip block RAMs that are directly integrated with the PE array. This merging eliminates the need for separate memory modules and complex external memory interfaces, reducing data communication time while keeping the hardware architecture manageable through functional integration.
Solution Approach 2:
The patent introduces on-chip block RAMs as intermediary buffers between the PE array and external memory systems. These intermediaries cache frequently accessed data locally, reducing the frequency and volume of data communication with external memory, thereby minimizing time loss without requiring a complete redesign of the external memory interface architecture.
Data Source
AI summary
A method of quantizing parameters of a neural network includes grouping a plurality of parameters of a neural network in a plurality of groups. Each group of the plurality of groups includes corresponding two or more parameters of the plurality of parameters. In an example, for each group, a corresponding quantization format is selected from a plurality of available quantization formats, such that a first quantization format selected for at least a first group is different from a second quantization format selected for at least a second group. For each group, individual parameters within the corresponding group are quantized using the quantization format selected for the corresponding group. The quantized parameters of the plurality of groups are stored in a memory.