Multi-core Neural Rendering Acceleration via Position Encoding

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Solution Overview

Problem

Conventional neural radiance field-based image rendering techniques face challenges in achieving real-time image rendering due to the large amount of data that needs to be processed, making them impractical for real-time applications.

Innovation Solution

A computing system comprising multiple computing cores that utilize position encoding logic and pipeline logics in series, capable of transforming coordinates and directions into high-dimensional representations, and executing computations associated with neural network layers in parallel to output intensity and color values of pixels, leveraging Fourier feature mapping and synchronous random access memory for efficient processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional neural radiance field-based image rendering techniques are used, then image rendering quality can be achieved, but real-time rendering speed cannot be achieved due to large amount of data processing required

Engineering Contradiction:
Improveimage rendering qualityVSAvoidrendering speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the image rendering task into multiple segments by splitting the image into multiple regions or tiles, each processed by separate computing cores. This segmentation allows parallel processing of different image portions simultaneously, significantly improving rendering speed while maintaining quality through distributed computation across multiple cores

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the rendering problem by introducing high-dimensional representations of coordinates and directions through position encoding logic. This dimensionality transformation enables the neural network to process spatial information more efficiently in a higher-dimensional space, achieving both quality preservation and speed improvement through enhanced feature representation

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If position encoding logic transforms coordinates and directions into high dimensional representations, then data processing efficiency is improved, but computational complexity increases

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidcomputational complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The position encoding logic performs preliminary transformation of coordinates and directions into high-dimensional representations before the main rendering computation. This preprocessing step organizes spatial information in advance, making subsequent neural network processing more efficient despite the increased dimensional complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The high-dimensional position encoding acts as an intermediary representation between raw coordinate data and the neural network processing. This intermediate representation facilitates more efficient computation by providing structured spatial features that the rendering network can process more effectively

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240281256A1Multi-core Acceleration of Neural Rendering
Publication Date: 2024.08.22 SHANGHAI TECH UNIV
  • US20240281256A1 patent drawing
  • US20240281256A1 patent drawing
  • US20240281256A1 patent drawing

AI summary

A computing core for rendering an image computing core comprises a position encoding logic and a plurality of pipeline logics connected in series in a pipeline. The position encoding logic is configured to transform coordinates and directions of sampling points corresponding to a portion of the image into high dimensional representations. The plurality of pipeline logics are configured to output, based on the high dimensional representation of the coordinates and the high dimensional representation of the directions, intensity and color values of pixels corresponding to the portion of the image in one pipeline cycle. The plurality of pipeline logics are configured to run in parallel.