Neural Network Semiconductor Circuit for Low-Power Product-Sum Operation

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Solution Overview

Problem

Artificial neural networks face challenges with increasing power consumption and heat generation due to the growing number of circuits, particularly in hierarchical networks, which affect circuit characteristics and are exacerbated by environmental temperature.

Innovation Solution

A semiconductor device with a hierarchical artificial neural network design incorporating specific circuit configurations, including transistors and capacitors, that manage current flow based on input potentials to reduce power consumption and temperature sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of circuits in the artificial neural network is increased to enhance processing capability, then the computational power and neural network scale are improved, but the power consumption and heat generation increase significantly

Engineering Contradiction:
Improvecomputational powerVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the artificial neural network into multiple layers (input layer, hidden layers, output layer) with distinct functional units. Each layer processes information independently, allowing the system to handle complex computations while managing power consumption through modular architecture. The segmentation of neural network functions across different circuit blocks enables scalable computational power without linearly increasing overall power consumption.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the number of circuits is increased to support larger neural networks, then the processing capability improves, but the heat generation increases and affects circuit characteristics

Engineering Contradiction:
Improveprocessing capabilityVSAvoidheat generation
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent implements temperature compensation mechanisms specifically in circuits that are more sensitive to temperature variations. Different circuit blocks use different compensation strategies based on their local temperature characteristics and sensitivity requirements. This localized approach allows the system to maintain processing capability while managing heat generation effects in critical areas without overheating the entire system.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If more circuits are added to increase neural network scale, then the computational accuracy and model complexity are improved, but the temperature sensitivity of circuits increases

Engineering Contradiction:
Improvecomputational accuracyVSAvoidtemperature sensitivity
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent incorporates temperature compensation circuits that use feedback mechanisms to detect and correct temperature-induced variations in circuit behavior. Temperature sensors monitor the thermal state of the circuit, and compensation circuits adjust operating parameters accordingly to maintain computational accuracy. This feedback loop allows the system to preserve precision even as the neural network scale and circuit complexity increase.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250365981A1Semiconductor device and electronic device
Publication Date: 2025.11.27 SEMICON ENERGY LAB CO LTD
  • US20250365981A1 patent drawing
  • US20250365981A1 patent drawing
  • US20250365981A1 patent drawing

AI summary

A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.