Deadlock-Free Neural Network Task Graph Scheduling on Multi-Core Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The asynchronous behavior of neural elements in a neural network on a multi-core processor leads to irregular execution and inter-core communication patterns, necessitating message buffers to avoid deadlock while minimizing storage space.
Innovation Solution
A method is proposed to map a task graph representing a neural network onto a multi-core processor by prioritizing nodes and edges, assigning these priorities to processor cores and NoC links, and using input buffers with capacities exceeding the sum of back-edge bounds to prevent deadlock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If message buffers are increased in capacity to avoid deadlock, then system reliability improves, but storage space requirements increase
Solution Approach 1:
The patent applies preliminary action by assigning priorities to nodes and edges in the task graph before execution, and by determining buffer capacities in advance based on back-edge bounds. This allows the system to prevent deadlock conditions before they occur rather than reacting to them, enabling modest buffer sizes to suffice when combined with the priority-based scheduling mechanism.
Solution Approach 2:
The patent changes parameters by introducing priority values for nodes and edges, and by calculating specific buffer capacity values based on back-edge bounds. These parameter assignments transform the scheduling problem into a prioritized execution model where resources are allocated dynamically based on priority levels rather than requiring uniformly large buffers for all tasks.
2Device complexity
If buffer capacity is minimized to reduce storage costs, then device complexity decreases, but the risk of deadlock increases
Solution Approach 1:
The patent transforms the buffer capacity problem by assigning priority parameters to nodes and edges and calculating minimum buffer capacities based on back-edge bounds. This parameter-based approach allows modest buffer sizes to prevent deadlock when combined with priority-aware scheduling, resolving the contradiction between small buffers and deadlock freedom.
Solution Approach 2:
The patent introduces priority assignments as an intermediary mechanism between task dependencies and buffer allocation. By mediating through priority levels and back-edge bound calculations, the system can allocate minimal buffers while maintaining deadlock freedom, as the priority mechanism coordinates resource usage without requiring large buffer capacities.
3Reliability
If priorities are assigned to all nodes and edges with strict ordering, then deadlock is prevented, but computational overhead increases
Solution Approach 1:
The patent reduces computational overhead by performing priority assignments and buffer capacity calculations in advance, before task execution begins. This preliminary action eliminates the need for complex real-time decisions during execution, as the priority-based scheduling rules are predetermined and can be executed with simple comparisons.
Solution Approach 2:
The patent simplifies the scheduling complexity by transforming it into a parameter assignment problem. By defining priority values and buffer capacities as static parameters determined beforehand, the system replaces complex runtime scheduling algorithms with simple parameter-based decision rules that are computationally efficient.
Data Source
AI summary
Examples in the present disclosure relate to the mapping of a task graph specifying a neural network on a multi-core processor. The multi-core processor exchanges messages in a message exchange network on chip (NoC). The task graph has a plurality of nodes interconnected by directed edges. For each node, a priority is assigned to the node and the node is assigned to a particular processor core of the multi-core processor. For each directed edge, a priority is assigned to the directed edge and the directed edge is assigned to an acyclic NoC path. The priority assigned to each node is a highest one of one or more priorities assigned to one or more of the directed edges that are incoming edges of the node. The priority assigned to each directed edge of the directed edges exceeds the priority of the node from which the directed edge is outgoing.