Neural Processing Tile Shuffling Nibbles to Skip Zero Weight Multiplications

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Solution Overview

Problem

Neural processors face challenges in minimizing power consumption and latency, particularly in applications involving image or video processing from moving vehicles and battery-powered mobile devices.

Innovation Solution

A mixed-precision neural processor design that includes a tile configuration with weight registers, multipliers, and a shuffler, which processes nibbles of weights and activations efficiently, skipping unnecessary multiplications and leveraging sparsity to reduce power consumption and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If all nibbles are processed through multiplication operations, then processing completeness is ensured, but power consumption increases and latency increases due to unnecessary multiplications with zero weights

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing completeness
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent extracts and removes unnecessary multiplication operations where weight nibbles are zero. The control logic detects zero weight nibbles and skips the corresponding multiplication and accumulation operations, extracting only the essential computational steps that contribute to the final result. This eliminates wasted energy on operations that would produce zero contributions anyway.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements skipping of unnecessary multiplication operations by detecting zero weight nibbles in advance. When a zero weight nibble is detected, the corresponding multiplication and accumulation steps are skipped entirely, allowing the processing to rush through the essential computations without being delayed by redundant operations.

Inventive Principle:
Principle #21Skipping (Rushing through)

2Loss of time

If all nibbles are processed through multiplication operations, then processing completeness is ensured, but latency increases due to unnecessary multiplications with zero weights

Engineering Contradiction:
ImprovelatencyVSAvoidprocessing completeness
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent extracts and removes unnecessary multiplication operations where weight nibbles are zero. The control logic detects zero weight nibbles and skips the corresponding multiplication and accumulation operations, extracting only the essential computational steps that contribute to the final result. This eliminates wasted time on operations that would produce zero contributions anyway.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements skipping of unnecessary multiplication operations by detecting zero weight nibbles in advance. When a zero weight nibble is detected, the corresponding multiplication and accumulation steps are skipped entirely, allowing the processing to rush through the essential computations without being delayed by redundant operations.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Loss of energy

If sparsity exploitation is implemented with shufflers and selective multiplication, then power consumption is reduced and latency is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidtile configuration complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the weight data into individual nibbles and processes them separately through the shuffler. Each nibble is independently examined for zero values, and the shuffler reorders them to group non-zero nibbles together. This segmentation enables fine-grained sparsity exploitation at the nibble level, allowing selective multiplication only for non-zero segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shuffler acts as an intermediary component between the weight register and the multiplication units. It receives weight nibbles, identifies zero values, and reorders the sequence to facilitate selective processing. This intermediary enables the control logic to efficiently skip zero multiplications while maintaining the computational pipeline.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12182577B2Neural-processing unit tile for shuffling queued nibbles for multiplication with non-zero weight nibbles
Publication Date: 2024.12.31 SAMSUNG ELECTRONICS CO LTD
  • US12182577B2 patent drawing
  • US12182577B2 patent drawing
  • US12182577B2 patent drawing

AI summary

A processor. In some embodiments, the processor includes: a first tile, the first tile being configured: to feed a first nibble from a third queue, through a first shuffler, to a first multiplier, and to multiply, in the first multiplier, the first nibble from the third queue by a first nibble of a third weight; to feed a second nibble from the third queue, through the first shuffler, to a second multiplier, and to multiply, in the second multiplier, the second nibble from the third queue by a second nibble of the third weight; and to feed a first nibble from a fourth queue, through the first shuffler, to a third multiplier, and to multiply, in the third multiplier, the first nibble from the fourth queue by a first nibble of a fourth weight.