Neural VMM Input and Output Circuits for Precise Weight Programming
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Solution Overview
Problem
Existing artificial neural networks face challenges in programming non-volatile memory cells with the precision required for high-performance information processing, particularly in achieving fine-tuning of synapse weights due to limitations in current hardware technologies, which affect the energy efficiency and scalability of analog neuromorphic memory systems.
Innovation Solution
The development of input function circuit blocks and output neuron circuit blocks coupled with vector-by-matrix multiplication arrays in an artificial neural network, utilizing CMOS technology and non-volatile memory arrays, enables precise programming and tuning of memory cells by allowing continuous and independent adjustment of charge on floating gates, enabling precise weight storage and adjustment of synapse weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If non-volatile memory cells are used for synapse weights in analog neuromorphic memory systems, then energy efficiency is improved, but manufacturing precision deteriorates due to difficulty in programming precise weight values
Solution Approach 1:
The programming process is divided into multiple stages: a first programming stage that programs a first portion of selected memory cells with a first voltage, and a second programming stage that programs a second portion of selected memory cells with a second voltage. This segmentation allows precise control of weight values by applying different voltages to different portions of cells, resolving the contradiction between energy efficiency and programming precision.
Solution Approach 2:
The patent implements dynamic programming by allowing memory cells to be programmed in different stages with different voltages based on their selection status. Selected memory cells receive appropriate voltage pulses during specific time periods, enabling precise weight adjustment. This dynamic approach overcomes the static limitation of traditional single-stage programming while maintaining energy efficiency.
2Productivity
If the number of synapses is increased to achieve high connectivity between neurons, then computational parallelism is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of weight storage and weight adjustment into a single non-volatile memory cell structure. The memory cell simultaneously stores synapse weights and allows in-situ programming through voltage application, eliminating the need for separate storage and programming circuits. This merging reduces device complexity while enabling high computational parallelism through increased synapse connectivity.
Solution Approach 2:
The non-volatile memory cells serve multiple functions: they store weight values, allow precise programming during training, and maintain their state for computation. This multi-functionality reduces the need for additional specialized components, thereby reducing overall system complexity while supporting high computational parallelism.
3Manufacturing precision
If precision programming of memory cells is achieved through multiple voltage stages, then manufacturing precision is improved, but use of energy increases
Solution Approach 1:
The patent applies local quality by directing different voltage levels to different portions of selected memory cells based on their specific programming needs. Only the necessary portions of cells receive high-voltage programming pulses, while other cells remain in low-power state. This localized approach achieves precise weight tuning while minimizing overall energy consumption during the programming process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the precision and efficiency of programming non-volatile memory cells, improving the energy efficiency and scalability of neural networks, allowing for more accurate and fine-tuned weight adjustments, thereby enhancing the performance of artificial neural networks in applications like facial recognition and other information processing tasks.
Implementation Method 1
Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs
Data Source
AI summary
Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.