Neuromorphic Device Synapse Weight Storage via Spin-Orbit Torque
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Solution Overview
Problem
Current semiconductor devices face limitations in energy consumption and system performance due to the Von Neumann architecture, particularly in data fetching between memory and processor, and struggle to express analog weight changes in synapses, which are essential for mimicking human brain functionality.
Innovation Solution
A neuromorphic device with unit weighting elements, including a fixed layer, a free layer, and a tunnel barrier layer, connected through drive transistors, allowing for resistance variation and multi-level data storage and readout by controlling magnetization direction and applying spin-orbit torque, enabling efficient storage and retrieval of synapse weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a cross-point array structure is used for memory, then area efficiency and power consumption are improved, but the ability to express analog weight changes is limited
Solution Approach 1:
The synapse weight storage is segmented into multiple bit units (e.g., 4 bits) within a single cross-point array cell. Each bit can be independently selected and controlled through drive transistors, allowing the device to represent multi-level analog weights (0-15 levels) while maintaining the area efficiency and low power consumption of the cross-point architecture.
2Manufacturing precision
If digital binary notation is used in semiconductor devices, then manufacturing precision is maintained, but the expression of analog weight varying between 0 and 1 is limited
Solution Approach 1:
The device uses resistance value changes in the cross-point memory cells to represent different weight levels. By controlling the resistance state (through magnetization switching in MTJ or phase change in PCM), the system can represent multiple discrete analog weight levels (e.g., 0-15) while maintaining precise digital control through binary selection signals, thus bridging digital manufacturing precision with analog weight expression.
3Loss of time
If hardware accelerators are placed adjacent to memory, then data fetching time is reduced, but system performance is still limited due to necessary data fetching
Solution Approach 1:
The invention merges the memory function and processor function into a single integrated device. The cross-point array simultaneously serves as storage for synapse weights and as a computing element that can perform arithmetic operations (multiplication and accumulation) in-place, eliminating the need for separate data fetching between memory and processor while achieving both low latency and high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The neuromorphic device effectively stores and reads out multi-level data simultaneously, reducing energy consumption and enhancing system performance by allowing for precise control of synapse weights, thereby overcoming limitations of traditional semiconductor architectures.
Implementation Method 1
applying spin-orbit torque, enabling efficient storage and retrieval of synapse weights
Implementation Method 2
a free layer of which a magnetization direction changes in parallel with or in anti-parallel with the fixed layer
Data Source
AI summary
A neuromorphic device including: a plurality of unit weighting elements connected to a bit line in a manner that shares the bit line, each of the plurality of unit weighting elements being connected to a source line and comprising a fixed layer of which a magnetization direction is fixed, a free layer of which a magnetization direction changes in parallel with or in anti-parallel with the fixed layer, and a tunnel barrier layer arranged between the fixed layer and the free layer and a plurality of drive transistors being selectively turned on according to a plurality of bit selection signals, respectively, and correspondingly driving the unit weighting elements, respectively, wherein the plurality of unit weighting elements have different resistances in such a manner as to correspond to bits, respectively, of a synapse weight.