Neuromorphic Arithmetic Device Zero-Bit Skip Mechanism

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Neuromorphic arithmetic devices that perform convolution based on neural networks experience decreased neural processing speed due to the use of analog MACs that perform 1-bit multiplication, leading to inefficiencies in arithmetic operations.

Innovation Solution

Incorporating an input monitoring circuit that skips arithmetic operations for bits identified as zeros in feature and weight data, utilizing a partial sum data generator and shift adder to generate result data based on non-zero partial sum data, thereby optimizing the arithmetic process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If analog MAC performs 1-bit multiplication to improve accuracy, then multiplication precision is improved, but neural processing speed decreases

Engineering Contradiction:
Improvemultiplication accuracyVSAvoidneural processing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The input monitoring circuit performs preliminary detection of zero bits in feature data and weight data before the main multiplication operation. By identifying zero bits in advance, the system can skip unnecessary multiplication and addition operations, thereby improving processing speed while maintaining accuracy for non-zero bits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of performing complete multiplication and addition operations for all bits, the invention applies partial action by skipping operations for zero bits. The system performs arithmetic operations only on non-zero bits, reducing the total number of operations required while preserving the accuracy of the final result

Inventive Principle:
Principle #16Partial or excessive action

2Measurement precision

If complete arithmetic operations are performed for all bits, then calculation accuracy is maintained, but power consumption increases and arithmetic speed decreases

Engineering Contradiction:
Improvecalculation accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The input monitoring circuit performs preliminary detection of zero bits before the main computation. This early detection allows the system to avoid unnecessary arithmetic operations for zero bits, reducing power consumption while ensuring accurate computation for non-zero bits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system discards unnecessary arithmetic operations for zero bits identified by the monitoring circuit. By skipping these redundant operations, the system recovers power that would have been consumed, while maintaining calculation accuracy through proper handling of non-zero bits

Inventive Principle:
Principle #34Discarding and recovering

3Measurement precision

If analog MAC performs complete MAC arithmetic, then result accuracy is improved, but arithmetic operation time increases

Engineering Contradiction:
Improveresult accuracyVSAvoidarithmetic operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The input monitoring circuit performs preliminary identification of zero bits in both feature data and weight data before the MAC operation. This allows the partial sum data generator to skip generating partial sum data for zero bits, reducing the number of addition operations required in the shift adder while maintaining result accuracy

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system applies partial action by performing MAC operations only for non-zero bits. The partial sum data generator skips arithmetic operations for zero bits, and the shift adder processes fewer partial sum data, thereby reducing arithmetic operation time while preserving result accuracy through proper handling of non-zero bit contributions

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11494630B2Neuromorphic arithmetic device and operating method thereof
Publication Date: 2022.11.08 ELECTRONICS & TELECOMM RES INST
  • US11494630B2 patent drawing
  • US11494630B2 patent drawing
  • US11494630B2 patent drawing

AI summary

The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.