Neuromorphic Cell Array Segmentation for Area Efficiency
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Solution Overview
Problem
In neuromorphic semiconductor devices, the inefficiency in circuit area usage and arithmetic efficiency per area is a challenge, especially during small-scale calculations, as the number of arithmetic cells required varies by layer in hierarchical neural networks, leading to unused cells and decreased efficiency.
Innovation Solution
A semiconductor device design incorporating a first and second cell array with converter circuits, allowing for efficient arrangement of arithmetic cells by matching the number of columns in each array, reducing unused cells and optimizing area usage through electrical connections and transistor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of arithmetic cells in a cell array is increased to support large-scale calculations, then the circuit can perform large-scale calculations, but the number of unused arithmetic cells increases during small-scale calculations, decreasing arithmetic efficiency per area
Solution Approach 1:
The cell array is divided into multiple sub-arrays (first sub-array, second sub-array, third sub-array, fourth sub-array) that can be independently activated. This segmentation allows the system to activate only the necessary number of sub-arrays for each calculation scale, reducing unused cells during small-scale calculations while maintaining large-scale calculation capability when all sub-arrays are activated.
Solution Approach 2:
The system dynamically configures the active cell array size by selectively activating different numbers of sub-arrays based on the calculation requirements. The control circuit adjusts which sub-arrays are operational, enabling the cell array to adapt its effective size dynamically rather than being fixed, thus optimizing arithmetic efficiency for each specific calculation task.
2Reliability
If the cell array size is fixed to accommodate the maximum number of neurons in one layer, then large-scale calculations can be performed, but circuit area is wasted when smaller calculations are performed
Solution Approach 1:
By segmenting the cell array into multiple sub-arrays, the system can activate only the necessary portion of the total cell array for each calculation task. This allows the physical circuit area to remain fixed (ensuring large-scale calculation capability), while the effective active area varies dynamically to match calculation requirements, reducing wasted area during small-scale operations.
3Area of stationary object
If analog current is used for arithmetic operation, then circuit scale can be smaller and circuit area can be small, but power consumption increases when analog current amount is increased
Solution Approach 1:
The system changes the operating parameters of the analog arithmetic circuit by dynamically adjusting the number of active arithmetic cells and the current amplitude based on calculation requirements. This allows the circuit to maintain small physical area while optimizing power consumption by using lower current amplitudes and fewer active cells for small-scale calculations, and higher current amplitudes with more cells for large-scale calculations.
Data Source
AI summary
A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively. The first converter circuit has a function of making data corresponding to a total amount of current flowing through the second and third wirings flow to the fourth and fifth wirings, respectively.