Neuromorphic Synapse Circuit Using Charge Readout for Low-Power Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional neuromorphic arithmetic devices face challenges in power consumption and chip size due to high capacitance in metal lines, which limits their application in fields where power consumption is a concern, especially as the amount of data processed increases.
Innovation Solution
The neuromorphic arithmetic device employs a charging/discharging circuit that stores and discharges charges induced by currents from synapse circuits, using a comparator to convert the voltage levels into digital values, reducing power consumption and simplifying the circuit structure by performing operations in an analog manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a digital arithmetic unit is used to quickly process massive data, then processing speed is improved, but power consumption and chip area increase
Solution Approach 1:
The patent replaces the digital arithmetic unit (mechanical/electronic switching system) with a neuromorphic arithmetic unit that uses continuous analog signals and neural network-inspired computation. This substitution allows parallel processing of massive data through synaptic weight adjustments and neural activation functions, achieving high processing speed while consuming less power because analog operations avoid the high-frequency switching and state transitions that consume significant energy in digital systems
2Speed
If a digital arithmetic unit is used to quickly process massive data, then processing speed is improved, but chip area increases
Solution Approach 1:
The patent merges multiple digital logic functions into a single neuromorphic arithmetic unit that performs computation through unified neural network operations. The synapse circuits integrate multiplication, accumulation, and activation functions in one analog structure, eliminating the need for separate digital arithmetic logic units, registers, and control circuits that would occupy large chip areas. This merging achieves high-speed parallel processing with compact circuit implementation
3Productivity
If the amount of data to be processed increases, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management through adaptive neural network operations where the neuromorphic arithmetic unit adjusts its computation intensity and activation patterns based on the amount and complexity of input data. When processing large datasets, the system uses sparse activation and selective synapse engagement to maintain high processing capability while dynamically scaling power consumption to match actual computational needs, avoiding the linear power increase characteristic of digital systems
4Productivity
If the number of synapse circuits increases, then processing capability is improved, but the size of current source required increases
Solution Approach 1:
The patent designs a universal current source architecture that serves multiple synapse circuits simultaneously through time-multiplexed operation and shared analog signal paths. The current source can dynamically allocate its output to different synapse circuits based on computational requirements, and uses analog signal aggregation to combine currents from multiple synapses into shared readout paths. This multi-functional design enables increased processing capability through more synapse circuits without proportionally increasing the size and power consumption of current source components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and chip size by minimizing the need for frequent oscillation of dendrite capacitors, allowing for efficient processing of large data sets while maintaining accurate digital representation of operation results.
Implementation Method 1
a charging/discharging circuit configured to store charges induced by the first current and the second current in a charging period, and discharge the charges in a discharging period
Implementation Method 2
a comparator configured to compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage
Data Source
AI summary
The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.