Neuromorphic Circuit Parasitic Capacitance Area Reduction
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Solution Overview
Problem
Classic neuromorphic circuits based on CMOS technology face issues with high power consumption and circuit area due to the use of large capacitors or digital solutions for implementing dynamic neurons and synaptic coefficients, which become exacerbated with increasing neural network complexity.
Innovation Solution
A neuromorphic circuit design utilizing resistive random access memory (RRAM) with ferro-tunnel junction elements and parasitic capacitance, where the common conductive line is charged by the sum of currents through resistive elements, and a comparator detects voltage exceeding a threshold to generate an output voltage, reducing the need for large capacitors and optimizing energy usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large capacitors are used to implement dynamic neurons and synaptic coefficients in conventional CMOS neuromorphic circuits, then the circuit can achieve the required dynamic behavior and memory functionality, but the circuit area and power consumption increase excessively
Solution Approach 1:
The patent extracts the capacitive functionality from separate large capacitor components and integrates it into the resistive memory element itself. The resistive memory element's parasitic capacitance is utilized to provide the necessary dynamic behavior, eliminating the need for external large capacitors and thereby reducing circuit area.
Solution Approach 2:
The resistive memory element serves multiple functions simultaneously: it acts as both the synaptic coefficient storage element and the capacitor for dynamic neuron behavior. This multi-functionality eliminates the need for separate dedicated capacitor components, reducing overall circuit area while maintaining required functionality.
2Reliability
If large capacitors are used to implement dynamic neurons and synaptic coefficients in conventional CMOS neuromorphic circuits, then the circuit can achieve the required dynamic behavior and memory functionality, but the power consumption increases excessively
Solution Approach 1:
The patent extracts the capacitive functionality from separate large capacitor components and integrates it into the resistive memory element itself. The resistive memory element's parasitic capacitance is utilized to provide the necessary dynamic behavior, eliminating the need for external large capacitors and thereby reducing circuit area.
Solution Approach 2:
The resistive memory element's parasitic capacitance is utilized to provide the necessary dynamic behavior, eliminating the need for external large capacitors and thereby reducing circuit area.
3Measurement precision
If digital solutions are used to store synaptic coefficients and implement neurons, then the circuit can achieve precise storage and computation, but the circuit area and power consumption increase
Solution Approach 1:
The resistive memory element's parasitic capacitance is utilized to provide the necessary dynamic behavior, eliminating the need for external large capacitors and thereby reducing circuit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces energy consumption and circuit area by leveraging the capacitive effects of resistive elements, enabling efficient operation of neuromorphic circuits with reduced complexity and power requirements.
Implementation Method 1
each comprising a first resistive memory element having an associated parasitic capacitance
Implementation Method 2
an output device configured to compare a first voltage on the first common conductive line to a threshold voltage and to generate an output voltage of the neural circuit based on the comparison
Implementation Method 3
the first resistive memory elements are ferrotunnel junction elements
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present description relates to a neural circuit (200) comprising: - a first plurality of synapses, each comprising a first resistive memory element having an associated parasitic capacitance, each of the first resistive memory elements being configured to supply a current to a first common conductive line (SL); and - an output device (206) configured to compare a first voltage on the first common conductive line to a threshold voltage (Vth) and to generate an output voltage (Vout) of the neural circuit on the basis of the comparison.