Neuromorphic Circuit Vertical Interconnects
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Solution Overview
Problem
Conventional artificial neural networks (ANNs) have limited connectivity between neurons, which hinders their ability to mimic the complex signal processing pathways of natural neural networks, and this limitation poses challenges in scaling and mass production, especially as device sizes shrink and complexity increases.
Innovation Solution
A neuromorphic circuit structure is developed, featuring vertically-extending neural nodes and an interconnect stack with multiple conducting lines and dielectric layers, where memory vias vertically couple the lines to create efficient signal pathways, allowing for increased connectivity and modular architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ANN infrastructure uses stacked memory elements to increase connections between neurons, then the number of connections increases, but the arrangement fails to comport with most device architectures as device scale shrinks
Solution Approach 1:
The patent transitions from planar horizontal connections to vertical three-dimensional connections using stacked conducting lines and memory vias. This dimensional change enables high connectivity while maintaining compatibility with standard vertical device fabrication processes, resolving the contradiction between connection density and manufacturability
Solution Approach 2:
The patent implements nested structures where memory vias are vertically embedded within dielectric layers, and multiple conducting lines are stacked in vertical tiers. This nesting approach maximizes connection density within the vertical space while conforming to conventional device architecture and fabrication capabilities
2Quantity of substance
If device scale and components continue to shrink, then integration density increases, but mass production at reasonable cost becomes more difficult
Solution Approach 1:
The patent segments the neural network infrastructure into modular repeating units: neural nodes, dielectric layers, conducting lines, and memory vias form standardized stacked modules. This segmentation enables scalable mass production through repetitive fabrication processes while achieving high integration density
Solution Approach 2:
The patent employs universal standardized components and fabrication processes that can be repeatedly applied across the entire device. The stacked architecture uses consistent dielectric materials, conducting line configurations, and via formation methods, enabling cost-effective mass production while maintaining high integration density
3Adaptability or versatility
If ANN designs and device hardware become more sophisticated, then processing capability increases, but mass production at reasonable cost is hindered
Solution Approach 1:
The patent achieves sophisticated processing capability through vertical stacking of multiple conducting lines and memory vias, creating three-dimensional signal pathways. This vertical architecture provides complex functionality while using standardized fabrication processes, reducing the mismatch between processing capability and manufacturing complexity
Data Source
AI summary
Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.