Control Plane Segmentation for Neuromorphic Data Transfer
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Solution Overview
Problem
Current neuromorphic platforms face challenges in achieving scalable, low-energy, and low-leakage control plane solutions for inter-array communication networks, leading to high area and energy overheads, which limits their scalability and flexibility.
Innovation Solution
The implementation of a control plane using high impedance devices with low leakage current, combined with TFT technology for parameter storage and wave pipelining, reduces the number of parallel control wires and dynamic energy consumption, while allowing for efficient parameter updating and data transfer through geometrical coding and shared delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional control plane organisation is used for inter-array communication, then data transfer functionality is achieved, but area overhead and energy consumption increase significantly
Solution Approach 1:
The control plane is segmented into multiple functional blocks distributed across different arrays. Each control array contains control logic for specific data arrays, enabling localized control and reducing the need for extensive inter-array control wiring. This segmentation maintains flexibility while reducing overall control plane area.
Solution Approach 2:
The patent introduces a third dimension by stacking control and data arrays in 3D integration. Control arrays are positioned above or below data arrays, with vertical interconnects providing control signals. This dimensional transition reduces lateral wiring area while maintaining control flexibility.
2Loss of energy
If high impedance devices with low leakage current are used, then energy consumption is reduced, but device complexity increases
Solution Approach 1:
The patent changes the electrical parameters of the control devices by using high impedance transistors with optimized threshold voltages and channel widths. This parameter optimization reduces leakage current while maintaining adequate drive strength, achieving lower energy consumption without significantly increasing device complexity.
3Loss of energy
If TFT technology is used for parameter storage, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The TFT-based parameter storage utilizes the inherent low-leakage properties of the TFT structure itself. The transistor acts as both the storage element and the control element, eliminating the need for separate leakage compensation circuits. This self-service approach reduces static energy consumption while the design incorporates tolerance to manufacturing variations.
4Productivity
If wave pipelining is implemented, then data transfer efficiency is improved, but control wire requirements increase
Solution Approach 1:
The patent merges data transfer and control functions into unified pipelines. Control signals and data signals share the same physical pathways where possible, and control operations are embedded within the data flow rather than being separate. This merging reduces the number of dedicated control wires while maintaining wave pipelining throughput benefits.
Data Source
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AI summary
A control plane (100) for controlling transfer of data to a data plane (120) comprises a number n of at least two memory cells (Dj) for each storing a digitally coded parameter value, each memory cell (Dj) having a data input electrode (101), a data output electrode (102) and a control electrode (103); n data input terminals (104) for each receiving a data input value and applying it to the data input electrode (101) of an associated memory cell (Dj) to which the data input terminal (104) is coupled, and n data output terminals, each coupled to a data output electrode of an associated memory cell (Dj). The control plane furthermore comprises a first delay line (81) comprising n or n-1 first delay elements (106j-1, 106j, 106j+1), the first delay line (81) being arranged for receiving a stream of control bit values, each first delay element controlling, based on its current control bit value, by means of an access control device (108j-1, 108j, 108j+1), the transfer of data received by a memory cell (Dj) via its associated data input electrode (104) to its associated data output electrode (105), thereby combining the data input value with the digitally coded parameter value stored in this associated memory cell (Dj), and a second delay line (80) comprising n or n-1 second delay elements (107j-1, 107j, 107j+1), the second delay line (80) being arranged for receiving an enabling signal for enabling the control bit values of the stream of control bit values in the first delay line (81) to be passed to the control electrode (103) of the associated memory cells (Dj), such that, when data in appears at the data input electrode (104) associated with a memory cell (Dj), it is transferred in a controlled and synchronised fashion to the associated output electrode (105), depending on the stream of control bit values and the enabling signal.