Neuromorphic Core Folding for Area-Efficient Neural Substrates
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Solution Overview
Problem
Conventional neuromorphic systems face challenges in achieving area efficiency while maintaining energy efficiency and parallelism, as they require dedicated hardware per neuron, which is contrary to CMOS methodologies, and suffer from increased energy consumption due to extensive wiring and sequential processing.
Innovation Solution
The implementation of a neurosynaptic core architecture with reconfigurable synapse weights, neuron parameters, and neuron biases, allowing for a folding process that optimizes area usage by exploiting repeated computation and logical connectivity, while maintaining energy efficiency through localized memory and event-driven computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated hardware is used per neuron to maintain parallelism and processing speed, then processing speed and parallelism are improved, but area efficiency deteriorates due to extensive wiring and hardware overhead
Solution Approach 1:
The patent implements a universal neuromorphic core that can be configured to perform different neuron types (e.g., LIF, Izhikevich, Hodgkin-Huxley) and synaptic operations through software control rather than dedicated hardware for each neuron type. This allows a single core design to handle multiple functions, reducing the area required compared to having dedicated hardware for each neuron while maintaining parallelism across multiple cores.
Solution Approach 2:
The patent transitions from a two-dimensional chip layout with extensive physical wiring to a hierarchical architecture where computational cores are arranged in a 2D mesh but neural connections are established through logical routing and buffering mechanisms. This adds temporal and logical dimensions to the connectivity, reducing the need for physical wiring density while maintaining full connectivity.
2Adaptability or versatility
If extensive wiring is used to achieve full connectivity between neurons, then parallelism and connectivity are improved, but energy consumption deteriorates due to increased wiring overhead
Solution Approach 1:
The patent extracts the connectivity management function from physical wiring into separate buffer components (input buffers, output buffers, and crossbar switches) that are co-located with each core. This separation allows connectivity to be managed locally at each core rather than requiring extensive point-to-point wiring between all neuron pairs, significantly reducing wiring overhead and energy consumption while maintaining full connectivity capabilities.
Solution Approach 2:
The patent introduces buffer structures as intermediary components between neurons and synapses. These buffers act as local memory structures that hold incoming spikes and outgoing signals, mediating the connectivity between cores without requiring direct physical wiring paths. This intermediary approach reduces the energy cost of maintaining extensive wiring while preserving full neural network connectivity.
3Device complexity
If sequential processing is used to simplify hardware design, then device complexity is reduced, but energy efficiency deteriorates due to loss of parallelism
Solution Approach 1:
The patent segments the neuromorphic system into multiple independent cores, each capable of parallel execution of neuron and synapse operations. Within each core, the segmentation of neurons into groups with shared resources (such as shared buffers and parameter storage) reduces individual core complexity while the multi-core architecture maintains overall parallelism and energy efficiency.
4Area of stationary object
If reconfigurable synapse weights and neuron parameters are implemented to optimize area usage, then area efficiency is improved, but device complexity increases due to folding and logical connectivity
Solution Approach 1:
The patent implements dynamic reconfiguration capabilities where synapse weights, neuron parameters, and connection topologies can be changed at runtime through software control. This dynamic approach allows the same physical hardware to adapt to different neural network architectures and computational tasks, optimizing area usage without requiring complex static wiring for all possible configurations. The reconfiguration is managed through programmable interfaces that control the buffer and crossbar structures.
Data Source
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AI summary
Architectures for multicore neuromorphic systems are provided. In various embodiments, a neural network description is read. The neural network description describes a plurality of logical cores. A plurality of precedence relationships are determined among the plurality of logical cores. Based on the plurality of precedence relationships, a schedule is generated that assigns the plurality of logical cores to a plurality of physical cores at a plurality of time slices. Based on the schedule, the plurality of logical cores of the neural network description are executed on the plurality of physical cores.