Neuromorphic Core Shared Synaptic Memory Multiplexing
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Solution Overview
Problem
Current neuromorphic processors face challenges in replicating the efficiency and density of biological neural networks while maintaining reliability and programmability, as they often sacrifice speed and plasticity for higher connectivity and precision.
Innovation Solution
The proposed neuromorphic processor architecture employs a mesh network of cores with time-multiplexed computation, shared memory resources, and synchronized global time steps to achieve efficient communication and computation, allowing for a high degree of connectivity and programmability while maintaining deterministic operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If neuromorphic processors use shared synaptic memory and time-multiplexed computation, then device complexity is reduced and wiring resources are saved, but manufacturing precision and reliability become more challenging to maintain
Solution Approach 1:
The patent merges synaptic weight storage and computation into a single shared memory structure (SYNAPSE_CFG) that is time-multiplexed across multiple dendritic compartments. Instead of dedicating separate memory resources to each compartment, the system combines these functions into one resource that serves multiple purposes through temporal multiplexing, thereby reducing overall wiring complexity while maintaining computational integrity through synchronized access protocols
Solution Approach 2:
The shared synaptic memory structure is designed to serve multiple dendritic compartments simultaneously through time-multiplexed access. The same memory resource performs multiple functions: storing weights for different compartments at different time steps, supporting both precision and sparse connectivity models, and enabling scalable network configurations. This multi-functionality reduces the total wiring resources needed while maintaining manufacturing feasibility through standardized memory interfaces
2Measurement precision
If neuromorphic processors increase connectivity and precision, then computational accuracy improves, but speed and plasticity are sacrificed
Solution Approach 1:
The system employs periodic time-multiplexed computation where synaptic weights are updated and accessed in synchronized global time steps. Each dendritic compartment processes information at different time intervals, allowing the system to maintain high precision through careful timing while achieving parallel processing speed. The periodic synchronization ensures that precision requirements are met through coordinated weight updates across all compartments without requiring all connections to be simultaneously active
Solution Approach 2:
The neuromorphic processor implements dynamic precision through variable-length synaptic weight representations and configurable precision modes. The system can dynamically adjust the precision level for different neural network layers and operations, allocating higher precision where needed and lower precision where acceptable, thereby maintaining computational accuracy for critical operations while improving overall processing speed through selective precision management
3Reliability
If neuromorphic processors use dedicated memory per dendritic compartment, then reliability improves, but device complexity and wiring resources increase
Solution Approach 1:
The patent combines multiple dedicated memory structures into a single shared synaptic memory (SYNAPSE_CFG) that is accessed by multiple dendritic compartments through time-multiplexed protocols. This merging reduces device complexity and wiring resources while maintaining computational reliability through synchronized access control and consistent memory interface standards that ensure data integrity across all compartments
Solution Approach 2:
The system introduces a centralized routing and control mechanism that mediates access between dendritic compartments and the shared synaptic memory. This intermediary layer manages time-multiplexed access, ensuring that reliability requirements are met through coordinated data transfer while reducing overall system complexity by providing a standardized interface between computation units and memory resources
Data Source
AI summary
An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.