Neuromorphic DRAM via Synaptic State Reinforcement
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Solution Overview
Problem
Conventional neuromorphic computing systems face performance mismatches due to the separation of processing units and memory, and custom-designed hardware is inflexible and costly to scale.
Innovation Solution
Represents neurons by memory rows in DRAM, where each bit represents a synapse, and uses inherent DRAM decay properties to emulate brain-like learning by reinforcing or degrading synaptic states, offloading neural processing from CPUs to DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional von Neumann architecture with separate processing units and memory is used, then device complexity is reduced and ease of manufacture is improved, but performance mismatch for neuromorphic applications occurs and productivity deteriorates
Solution Approach 1:
The patent merges memory and processing functions by implementing neuromorphic computing directly within the DRAM array. Memory rows represent neurons and memory cells represent synapses, allowing the memory structure to perform neural network computations natively, thereby eliminating the performance mismatch between separate memory and processing units while maintaining manufacturing simplicity
Solution Approach 2:
The DRAM array is designed to serve multiple functions: traditional data storage and neuromorphic computing. By representing neurons as memory rows and synapses as memory cells, the same hardware infrastructure supports both conventional memory operations and brain-inspired computational tasks, improving productivity without requiring entirely separate specialized hardware
2Productivity
If custom designed neuromorphic hardware is used, then neuromorphic computing performance is improved, but device complexity increases and ease of manufacture deteriorates due to costly design and manufacturing requirements
Solution Approach 1:
The invention enables standard DRAM hardware to perform neuromorphic computing by reinterpreting memory structures as neural network components. This approach allows existing manufacturing processes and hardware designs to be used without costly custom fabrication, while still achieving improved neuromorphic computing performance through the novel mapping of neurons to memory rows and synapses to memory cells
Solution Approach 2:
The DRAM array performs neuromorphic computations using its inherent structure and operations without requiring external specialized processing units. The memory cells naturally perform synaptic weight storage and multiplication through standard read operations, and the decay properties of DRAM can be leveraged to emulate biological neuron behavior, allowing the system to serve its own computational needs
Data Source
AI summary
A computer-implemented method is provided for neuromorphic computing in a Dynamic Random Access Memory (DRAM). The method includes representing one or more neurons by memory rows in the DRAM. Each bit in any of the memory rows represents a single synapse. The method further includes responsive to activating a given one of the neurons, reinforcing an associated synaptic state of a corresponding one of the memory rows representing the given one of the neurons. The method also includes responsive to inhibiting the given one of the neurons, degrading the associated synaptic state of the corresponding one of the memory rows representing the given one of the neurons.