Neuromorphic Computing Architecture with Dynamic Context Allocation

Solution Overview

Problem

Conventional neuromorphic computing systems are limited in executing neural algorithms with a greater number of neurons than available neuron circuits, leading to increased power and time requirements due to the need for data transfer between systems, which compromises their power and time advantages.

Innovation Solution

A neuromorphic computing system with a configurable neural architecture and a resource allocation system that reconfigures neuron circuits and synapse connections to execute neural algorithms by identifying subgraphs and processing them serially, allowing the system to handle algorithms with more neurons than available circuits by using delay buffers and timing data to synchronize outputs across layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional neuromorphic computing systems execute neural algorithms with more neurons than available neuron circuits by transferring data between systems, then the algorithm can be executed, but power and time requirements increase

Engineering Contradiction:

Improveability to execute algorithms with more neurons than available circuitsVSAvoidpower requirements

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the neural algorithm execution into multiple time steps, where each time step processes a portion of the neurons. The neuron circuits are reused across different time steps to represent different neurons in different layers, rather than requiring all neurons to be simultaneously represented by dedicated circuits. This segmentation in time allows the system to handle algorithms with more neurons than available circuits without external data transfer.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the computation by executing neural algorithms over multiple time steps. Instead of requiring all neurons to be represented spatially at once, the system uses the time dimension to sequentially represent different neurons and layers. This dimensional transformation from purely spatial to spatio-temporal computation enables the system to overcome its limited neuron circuit count.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If conventional neuromorphic computing systems execute neural algorithms with more neurons than available neuron circuits by transferring data between systems, then the algorithm can be executed, but execution time increases

Engineering Contradiction:

Improveability to execute algorithms with more neurons than available circuitsVSAvoidexecution time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the neural algorithm execution into multiple time steps, where each time step processes a portion of the neurons. The neuron circuits are reused across different time steps to represent different neurons in different layers, rather than requiring all neurons to be simultaneously represented by dedicated circuits. This segmentation in time allows the system to handle algorithms with more neurons than available circuits without external data transfer.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent maintains continuous useful action by keeping the neuron circuits actively computing throughout the execution process. Instead of transferring data externally between systems (which would introduce idle time), the system continuously reconfigures and reuses the same physical circuits to represent different neurons across time steps, eliminating external transfer delays and maintaining uninterrupted computation.

Inventive Principle:

Principle #20Continuity of useful action

3Adaptability or versatility

If neuron circuits are reused across different layers and time steps, then the system can handle more neurons than available circuits, but the system requires reconfiguration mechanisms

Engineering Contradiction:

Improveability to represent more neurons than physical circuitsVSAvoidconfiguration complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements universality by designing neuron circuits that can serve multiple functions across different time steps and layer representations. The same physical neuron circuits are configured to represent different neurons in different layers at different times, making the hardware universal rather than dedicated. This multi-functionality reduces the total number of physical circuits needed while accepting the trade-off of reconfiguration complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic reconfiguration capabilities that allow the system to adapt its neural architecture on-the-fly. The connection weights and circuit configurations are dynamically adjusted between time steps to represent different portions of the neural algorithm. This dynamic adaptability enables the system to handle diverse algorithm sizes and structures, though it requires sophisticated control mechanisms to manage the reconfiguration process.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10970630B1Neuromorphic computing architecture with dynamically accessible contexts

Publication Date: 2021.04.06 NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA LLC

AI summary

Various technologies pertaining to allocating computing resources of a neuromorphic computing system are described herein. Subgraphs of a neural algorithm graph to be executed by the neuromorphic computing system are identified. The subgraphs are each executed by a group of neuron circuits serially. Output data generated by execution of the subgraphs are provided to the same or a second group of neuron circuits at a same time or with associated timing data indicative of a time at which the output data was generated. The same or second group of neuron circuits performs one or more processing operations based upon the output data.