Neuromorphic Error Corrector for Synapse Learning Accuracy
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Solution Overview
Problem
Neuromorphic devices lack an effective method to optimize synapse resistance changes and correct errors in their learning processes, which affects their performance and accuracy.
Innovation Solution
A neuromorphic device with an integrated error correction system, including an error detector and correction signal generator, that uses post-synaptic neuron outputs to adjust pre-synaptic neuron inputs and synapse training signals, allowing for real-time error correction and optimized learning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synapse resistance changes are used for learning in neuromorphic devices, then learning capability is achieved, but learning accuracy and error correction are insufficient
Solution Approach 1:
The patent implements feedback mechanisms where post-synaptic neurons send error signals back to pre-synaptic neurons and synapses. The error corrector uses the difference between expected and actual output values to generate correction signals that adjust synapse resistance, creating a closed-loop system that continuously improves learning accuracy through iterative error correction.
Solution Approach 2:
The patent replaces traditional mechanical or electronic error correction mechanisms with neuro-mimicking circuits that use analog voltage signals and resistance changes. The error corrector circuit uses voltage division, integration, and comparison operations to generate correction signals, substituting digital error correction with analog neuromorphic processing that mimics biological error correction.
2Reliability
If traditional error correction methods are added to neuromorphic devices, then error correction capability improves, but device complexity increases
Solution Approach 1:
The patent merges the error correction function with the existing neuromorphic circuit architecture. The error corrector is integrated into the post-synaptic neuron structure, sharing circuit elements like integrators and comparators with the learning function. This consolidation allows error correction to be performed without adding separate dedicated correction circuits, thereby reducing overall device complexity.
Solution Approach 2:
The patent designs universal circuits that perform multiple functions. The post-synaptic neuron circuit serves both as the learning output unit and as the error detection unit. The same integrator and comparator circuits used for learning also participate in error calculation, allowing one circuit structure to fulfill multiple roles in both learning and error correction processes.
3Productivity
If continuous learning optimization is performed in neuromorphic devices, then learning speed increases, but power consumption increases
Solution Approach 1:
The patent implements periodic learning updates rather than continuous optimization. The error corrector operates in discrete steps, performing error calculation and synapse adjustment only when necessary (e.g., when error exceeds a threshold or at specific time intervals). This periodic operation reduces unnecessary computational activity and associated power consumption while maintaining effective learning speed.
Solution Approach 2:
The patent enables the neuromorphic device to perform self-correction without external intervention. The error corrector automatically detects errors and generates correction signals to adjust synapse resistance values, allowing the system to optimize its own learning process autonomously. This self-service capability eliminates the need for power-intensive external control circuits while maintaining fast learning through continuous autonomous optimization.
Data Source
AI summary
A neuromorphic device includes a pre-synaptic neuron, a synapse electrically coupled to the pre-synaptic neuron through a row line, and a post-synaptic neuron electrically coupled to the synapse through a column line. The post-synaptic neuron includes an integrator, a comparator, and an error corrector including an error detector and a correction signal generator. The comparator and the error corrector receive an output of the integrator.