3D Neuromorphic System With Double-Sided Interposer
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Solution Overview
Problem
Prior art neuromorphic computing platforms lack flexibility and efficiency in memory bandwidth, limiting their ability to simulate complex neural networks effectively.
Innovation Solution
A three-dimensional (3D) neuromorphic computing system with a logic wafer, a double-sided interposer for signal communication, and 3D memory modules, along with fully integrated voltage regulators and power modules, enabling high-memory bandwidth and flexible scalability by mimicking brain connectivity and using software-defined neurons and synaptic connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog chips are used to simulate spiking neurons, then neuromorphic computing functionality is achieved, but flexibility and memory bandwidth are insufficient
Solution Approach 1:
The patent replaces analog neuromorphic chips with a digital computing system using discrete logic circuits and software-defined neurons. This substitution enables flexible reconfiguration of neural network architectures through software while achieving high memory bandwidth through parallel digital operations across multiple processors and memory modules.
Solution Approach 2:
The patent transitions from two-dimensional chip-based architecture to a three-dimensional system integrating logic wafers, interposers, and memory modules in vertical stacks. This 3D integration dramatically increases memory bandwidth by providing multiple simultaneous access paths while maintaining flexibility through software control of the modular architecture.
2Productivity
If memory bandwidth is increased through 3D integration, then simulation capability improves, but system complexity increases
Solution Approach 1:
The patent divides the neuromorphic system into modular segments: logic wafers containing processors, interposers for interconnection, and memory modules. Each segment is independently designed and manufactured, then assembled into a 3D stack. This segmentation achieves high memory bandwidth through parallel access while managing complexity through standardized interfaces and modular design.
Solution Approach 2:
The patent introduces interposers as intermediary components between logic wafers and memory modules. These interposers provide standardized connection interfaces, signal routing, and physical alignment features, thereby simplifying the integration process and reducing system complexity despite the 3D modular architecture.
3Adaptability or versatility
If software-defined neurons are used, then adaptability improves, but computational overhead increases
Solution Approach 1:
The patent implements event-driven spiking neuron computation where software-defined neurons only perform computational operations when triggered by incoming spikes. This periodic, event-based execution pattern reduces computational overhead compared to continuous processing, while maintaining high adaptability through software reconfiguration of neural network parameters and architectures.
Data Source
AI summary
Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.