Neuromorphic LUT Architecture for Fast Synaptic Weight Updates
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Solution Overview
Problem
Existing neuromorphic systems face challenges in achieving energy-efficient, real-time on-chip learning and synaptic weight updates due to limitations in reconfigurability and high clock speeds required by address event representation protocols, leading to synaptic redundancy and delays in inverse lookup.
Innovation Solution
A neuromorphic device employing a lookup table (LUT)-based reconfigurable neural network architecture that utilizes a synapse block, neuron block, and topology block to enable fast spike routing and synaptic weight updates through parallel search and partitioned LUT modules, allowing for efficient on-chip learning and inference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a lookup table (LUT) based reconfigurable neural network architecture is used, then synaptic weight updates and event routing speed are improved, but device complexity increases due to the need for parallel LUT modules and partitioned address management
Solution Approach 1:
The LUT is divided into multiple partitions, with each partition handled by a separate parallel LUT module. The synapse address is segmented into a first address for selecting the partition and a second address for indexing within the partition. This segmentation enables parallel processing of synaptic weight updates while maintaining manageable complexity in each individual module.
Solution Approach 2:
The address space is extended from a single-dimension linear address to a two-dimensional address space consisting of a first address (partition selector) and a second address (index within partition). This dimensional transformation allows the system to parallelize the lookup process across multiple LUT modules while keeping each module's internal structure simple and manageable.
2Speed
If high clock speeds are used to achieve real-time processing in address event representation protocols, then processing speed is improved, but energy consumption increases
Solution Approach 1:
By dividing the LUT into multiple partitions handled by parallel modules, the system can process multiple synaptic weight updates simultaneously in a single clock cycle. This parallel segmentation reduces the required clock speed for achieving real-time processing, thereby lowering energy consumption while maintaining processing throughput.
Solution Approach 2:
The LUT is pre-configured with synaptic weight values and connection information during idle periods or between processing cycles. This preliminary action allows the high-speed lookup and update operations to proceed without requiring continuous high clock speeds, reducing overall energy consumption while maintaining real-time processing capability.
3Ease of operation
If a single large LUT is used to store all synapse information, then memory access is simplified, but synaptic redundancy increases and search efficiency decreases
Solution Approach 1:
The large LUT is segmented into multiple smaller partitions, each stored in a separate parallel LUT module. This segmentation eliminates synaptic redundancy by distributing unique synapse information across partitions, while the first address (partition selector) and second address (index) mechanism maintains simple and systematic memory access patterns.
Solution Approach 2:
The single large LUT is transformed into a multi-dimensional memory structure with partitions along one dimension and indices within partitions along another. This dimensional organization reduces redundancy by efficiently packing synapse information while maintaining straightforward access through the two-component address system.
Data Source
AI summary
A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.