Neuromorphic Memory Cell Array Integrating Synapse Weights
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Solution Overview
Problem
As the number of layers and artificial neurons in artificial neural networks increases, existing technologies face challenges in efficiently storing and implementing synapse weights and biases on semiconductor chips, requiring high integration and low power solutions.
Innovation Solution
A memory-based neuromorphic device is developed, incorporating a memory cell array and neuron circuits with integrators and activation circuits to sum and process weights, allowing for efficient storage and reuse of neuron connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of layers and artificial neurons in artificial neural networks increases, then the computational capability and accuracy of the neural network are improved, but the storage requirements for synapse weights and biases increase, leading to higher device complexity and power consumption
Solution Approach 1:
The patent merges the weight storage function and the neuron computation function into a single integrated structure. The memory cell array stores synapse weights while being directly connected to neuron circuits that perform computational operations, eliminating the need for separate weight storage and computation units. This integration reduces overall device complexity while maintaining the ability to handle increased numbers of layers and neurons.
Solution Approach 2:
The memory cell array serves multiple functions simultaneously: it stores synapse weights for different neural network layers, provides read access to weight values for computational operations, and maintains data persistence across operations. The neuron circuits also perform multiple functions including weight retrieval, summation of weighted inputs, and activation function application. This multi-functionality reduces the total component count and device complexity.
2Productivity
If the number of layers and artificial neurons increases, then the neural network's ability to process complex tasks is improved, but the power consumption for storing and processing synapse weights increases
Solution Approach 1:
By merging weight storage and computation into an integrated architecture, the patent eliminates the energy overhead of transferring weight data between separate memory and processing units. The neuron circuits access weights directly from the memory cell array through localized connections, reducing communication energy consumption while enabling processing of complex tasks with multiple layers and neurons.
Solution Approach 2:
The patent segments the neural network into modular units where each neuron circuit is closely coupled with its associated weight storage in the memory cell array. This segmentation allows for localized computation and weight access, reducing the overall power consumption by minimizing data transfer distances and enabling independent operation of neural network layers.
3Measurement precision
If more synapse weights and biases need to be stored, then the accuracy of the neural network is improved, but the integration density requirements increase
Solution Approach 1:
The integration of weight storage and neuron computation allows for efficient utilization of chip area. The memory cell array is directly connected to neuron circuits, eliminating the need for separate weight storage regions and reducing interconnect area. This merging enables higher integration density while maintaining the storage capacity needed for accurate neural network operation with multiple layers and neurons.
Solution Approach 2:
The patent employs a three-dimensional stacked architecture where memory cell arrays and neuron circuits are arranged in vertical layers. This dimensional transition from planar to vertical organization increases the effective storage and computation capacity within the same chip footprint, allowing more synapse weights to be stored and processed without proportionally increasing the chip area.
Data Source
AI summary
A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.