Neuromorphic Memory Circuit Bi-Directional Information Flow
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Solution Overview
Problem
Current neuromorphic memory circuits lack bi-directional information flow, limiting their ability to implement backward transmission of information, which is essential for efficient training of synaptic weights in artificial neural networks.
Innovation Solution
A neuromorphic memory circuit with a three-transistor, one-resistor structure that separates forward and backward LIF, and STDP functionalities, utilizing programmable resistive memory elements and capacitors to enable bi-directional information flow through axon and dendrite drivers, allowing for both forward and backward propagation of pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current neuromorphic memory circuit structure is used, then device complexity is reduced, but bi-directional information flow capability is lost
Solution Approach 1:
The circuit is segmented into distinct functional units: axon driver, dendrite driver, postsynaptic capacitor, presynaptic capacitor, and programmable resistive memory element. Each segment handles specific aspects of forward or backward propagation, enabling bi-directional information flow while maintaining manageable complexity through modular organization.
Solution Approach 2:
The programmable resistive memory element serves multiple functions: it acts as a synapse for forward propagation, a programmable resistor for controlling discharge paths, and a storage element for synaptic weights. This multi-functionality enables bi-directional operation without proportionally increasing overall device complexity.
2Manufacturing precision
If forward and backward LIF and STDP functionalities are combined in single circuit paths, then device complexity is minimized, but information flow control precision is reduced
Solution Approach 1:
Forward LIF, backward LIF, forward STDP, and backward STDP functionalities are separated into distinct circuit paths with dedicated transistors and capacitors. This segmentation enables precise control over each information flow direction and temporal dynamics without interference between functions.
Solution Approach 2:
Different parts of the circuit are optimized for specific functions: the postsynaptic capacitor and its associated transistor are optimized for forward propagation control, while the presynaptic capacitor and its transistor are optimized for backward propagation control. This local optimization enables precise information flow control in each direction.
3Productivity
If bi-directional information flow is enabled, then synaptic weight training efficiency is improved, but device complexity increases
Solution Approach 1:
The circuit implements feedback mechanisms where backward propagation pulses carry error signals from the postsynaptic neuron to the presynaptic neuron, enabling synaptic weight adjustment. The programmable resistive memory element provides feedback control by adjusting its resistance based on spike timing differences, implementing STDP learning rules efficiently.
Solution Approach 2:
The neuromorphic memory circuit performs synaptic weight training autonomously through self-organizing mechanisms. The STDP functionality automatically adjusts synaptic weights based on spike timing correlations without external intervention, enabling efficient learning while maintaining relatively simple circuit architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient training of synaptic weights by allowing backward transmission of information, enhancing the capability of artificial neural networks to simulate biological brain functions and improve learning and memory processes.
Implementation Method 1
a programmable resistive memory element
Implementation Method 2
a postsynaptic capacitor configured to build up a forward propagation LIF charge over time
Implementation Method 3
a presynaptic capacitor configured to build up a back propagation LIF charge over time
Implementation Method 4
A first transistor, electrically coupled to the postsynaptic capacitor and the programmable resistive memory element, activates a first discharge path from the postsynaptic capacitor through the programmable resistive memory element
Implementation Method 5
A second transistor, electrically coupled to the presynaptic capacitor and the programmable resistive memory element, activates a second discharge path from the presynaptic capacitor through the programmable resistive memory element
Data Source
AI summary
A neuromorphic memory circuit including a programmable resistive memory element, an axon LIF pulse generator to generate an axon LIF pulse, a back propagation pulse generator to generate a back propagation pulse, a postsynaptic capacitor configured to build up a forward propagation LIF charge over time, and a presynaptic capacitor configured to build up a back propagation LIF charge over time. A first transistor activates a first discharge path from the postsynaptic capacitor through the programmable resistive memory element when the axon LIF pulse generator generates the axon LIF pulse. A second transistor activates a second discharge path from the presynaptic capacitor through the programmable resistive memory element when the back propagation pulse generator generates the back propagation pulse.