Neuromorphic Memory Crossbar Array Expansion for Non-Ideality Compensation
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Solution Overview
Problem
Neuromorphic memory devices face non-ideality issues that affect the accuracy and efficiency of computations, particularly in performing dot products and matrix-vector multiplications.
Innovation Solution
The method involves expanding the initial block of a neuromorphic memory device's crossbar array by adding memory elements to the wordlines and bitlines, allowing for a predefined total conductance and offset current, which compensates for non-idealities and improves computation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wordline expansion is performed by adding memory elements to enable predefined total conductance, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
The crossbar array is divided into an initial block and additional blocks. The initial block contains the essential memory elements for computing dot products, while additional blocks are added only when needed to compensate for non-idealities. This segmentation allows the system to maintain simplicity for basic operations while providing enhanced accuracy when required.
Solution Approach 2:
The conductance values of memory elements are dynamically adjusted through programming to achieve predefined total conductance in expanded wordlines. By changing the conductance parameter of additional memory elements, the system compensates for capacitive discharging effects and improves computation accuracy without permanently increasing device complexity.
2Measurement precision
If bitline expansion is performed by adding memory elements to generate predefined offset current, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
The bitline structure is segmented into initial bitlines and additional bitlines. The initial bitlines handle the primary computation, while additional bitlines with offset current generation are added only when compensation for non-idealities is needed, maintaining simplicity for basic operations.
Solution Approach 2:
Additional memory elements are introduced as intermediary components between the initial block and the readout circuitry. These intermediary elements generate offset currents that compensate for capacitive discharging effects, improving accuracy without directly increasing the complexity of the core computation path.
3Measurement precision
If additional memory elements are added to compensate for non-ideality, then signal-to-noise ratio is improved, but manufacturing complexity increases
Solution Approach 1:
The additional memory elements are programmed with predefined conductance values during manufacturing to compensate for known non-idealities such as capacitive discharging. This preliminary action allows the system to achieve improved signal-to-noise ratio while keeping the manufacturing process systematic and manageable through standardized programming procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the computation accuracy and signal-to-noise ratio by controlling the conductance and offset currents, thereby mitigating errors caused by capacitive discharging and improving the linearity of read current signals.
Implementation Method 1
resistive memory elements coupled between the wordlines and the bitlines at junctions formed by the wordlines and the bitlines
Implementation Method 2
the adding comprising programming the added memory elements to enable a predefined total conductance in the expanded worldline segment
Implementation Method 3
the adding comprising programming the added memory elements to generate a predefined offset current in the expanded bitline segment
Data Source
AI summary
The present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. The neuromorphic memory device comprising a crossbar array of wordlines and bitlines. The crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. The device is configured for applying a set of inputs to the initial wordlines for performing dot products. The method comprises: performing at least one of: wordline expansion or bitline expansion of the block. The set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. The currents flowing in the bitlines of the expanded block may be measured. The dot products may be determined using the measured currents.